Ð þí\98UÜ(]U¤"ad,tecad,tamontennvidia,tegra20&+7Avionic Design Tamonten Evaluation Carrierchosen=serial0:115200n8aliasesI/i2c@7000d000/tps6586x@34N/rtc@7000e000S/serial@70006300memory[memoryg host1x@50000000!nvidia,tegra20-host1xsimple-busgP@kACv}„host1x TTmpe@54040000nvidia,tegra20-mpegT kDv<}<„mpevi@54080000nvidia,tegra20-vigT kEvd}„viepp@540c0000nvidia,tegra20-eppgT  kFv}„eppisp@54100000nvidia,tegra20-ispgT kGv}„ispgr2d@54140000nvidia,tegra20-gr2dgT kHv}„2dgr3d@54180000nvidia,tegra20-gr3dgTv}„3ddc@54200000nvidia,tegra20-dcgT  kIvy —dcparent}„dc£rgb ¯disableddc@54240000nvidia,tegra20-dcgT$ kJvy —dcparent}„dc£rgb ¯disabledhdmi@54280000nvidia,tegra20-hdmigT( kKv3u —hdmiparent}3„hdmi¯okay¶ÁÌ ßotvo@542c0000nvidia,tegra20-tvogT, kLvf ¯disableddsi@54300000nvidia,tegra20-dsigT0v0}0„dsi ¯disabledtimer@50040600arm,cortex-a9-twd-timer&gP  k v„interrupt-controller@50041000arm,cortex-a9-gicgPPï&cache-controller@50043000arm,pl310-cachegP0  .>Linterrupt-controller@60004000nvidia,tegra20-ictlr g`@`AP`BP`CPï&timer@60005000nvidia,tegra20-timerg`P`0k)*vclock@60006000nvidia,tegra20-carg``Xeflow-controller@60007000nvidia,tegra20-flowctrlg`pdma@6000a000nvidia,tegra20-apbdmag` Àkhijklmnopqrstuvwv"}"„dmar ahb@6000c000nvidia,tegra20-ahbg`Àgpio@6000d000nvidia,tegra20-gpiog`ÐTk !"#7WY}‰ïapbmisc@70000800nvidia,tegra20-apbmiscgpdppinmux@70000014nvidia,tegra20-pinmux gpp€ p ph¨™default§pinmuxata±ata½ideatb ±atbgmagme½sdio4atc±atc½nandatd#±atdategmbgmdgpuspiaspibspic½gmicdev1±cdev1 ½plla_outcdev2±cdev2 ½pllp_out4crtp±crtp½crtcsus±csus½vi_sensor_clkdap1±dap1½dap1dap2±dap2½dap2dap3±dap3½dap3dap4±dap4½dap4dta±dtadtd½sdio2dtb ±dtbdtcdte½rsvd1dtf±dtf½i2c3gmc±gmc½uartdgpu7±gpu7½rtckgpv±gpvslxaslxk½pciehdint±hdint½hdmii2cp±i2cp½i2cpirrx ±irrxirtx½uartakbca±kbcakbcbkbcckbcdkbcekbcf½kbclcsn·±lcsnld0ld1ld2ld3ld4ld5ld6ld7ld8ld9ld10ld11ld12ld13ld14ld15ld16ld17ldcldilhp0lhp1lhp2lhslm0lm1lpplpw0lpw1lpw2lsc0lsc1lscklsdalsdilspilvp0lvp1lvs ½displayaowc±owcspdispdouac½rsvd2pmc±pmc½pwr_onrm±rm½i2c1sdb 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ti,tps6586xg4 kV>}‰Y d s ‚ ‘ ¡ ± À Ñ regulatorssysàvdd_sysï sm0àvdd_sys_sm0,vdd_coreO€O€ïsm1àvdd_sys_sm1,vdd_cpuB@B@ïsm2àvdd_sys_sm2,vin_ldo*8u 8u ï ldo0àvdd_ldo0,vddio_pex_clk2Z 2Z ldo1àvdd_ldo1,avdd_pll*ÈàÈàïldo2àvdd_ldo2,vdd_rtcO€O€ldo3àvdd_ldo3,avdd_usb*2Z 2Z ïldo4àvdd_ldo4,avdd_osc,vddio_sysw@w@ïldo5àvdd_ldo5,vcore_mmc+|Ð+|Ðldo6àvdd_ldo6,avdd_vdac+|Ð+|Ðldo7àvdd_ldo7,avdd_hdmi2Z 2Z ldo8àvdd_ldo8,avdd_hdmi_pllw@w@ldo9àvdd_ldo9,vdd_ddr_rx,avdd_cam+|Ð+|Ðïldo_rtc àvdd_rtc_out2Z 2Z ïtemperature-sensor@4c onnn,nct1008gLspi@7000d400nvidia,tegra20-slinkgpÔ k;v)})„spié  îrxtx ¯disabledspi@7000d600nvidia,tegra20-slinkgpÖ kRv,},„spié  îrxtx ¯disabledspi@7000d800nvidia,tegra20-slinkgpØ kSv.}.„spié  îrxtx ¯disabledspi@7000da00nvidia,tegra20-slinkgpÚ k]vD}D„spié  îrxtx ¯disabledkbc@7000e200nvidia,tegra20-kbcgpâ kUv$}$„kbc ¯disabledpmc@7000e400nvidia,tegra20-pmcgpä vn —pclkclk32k_in3K_ˆxˆª#Ãmemory-controller@7000f000nvidia,tegra20-mcgpð$pð<Ä kMiommu@7000f024nvidia,tegra20-gartgpð$Xmemory-controller@7000f400nvidia,tegra20-emcgpôfuse@7000f800nvidia,tegra20-efusegpøv'—fuse}'„fusepcie@80003000nvidia,tegra20-pcie[pcig€0€8 äpadsaficskbc îintrmsiþ bÿx‚€€‚€€‚‚  ¨¨vFHv—pexafipll_e}FHJ„pexafipcie_x¯okay)*9M^pci@1,0[pcis‚€gÿ¯okay†pci@2,0[pcis‚€gÿ ¯disabled†usb@c5000000nvidia,tegra20-ehciusb-ehcigÅ@ k—utmi v}„usb·Ñ ¯disabledusb-phy@c5000000nvidia,tegra20-usb-phygÅ@Å@—utmi vj—regpll_utimerutmi-pads}„usbutmi-pads Ü ö "8 J^r ¯disabledusb@c5004000nvidia,tegra20-ehciusb-ehcigÅ@@ k—ulpiv:}:„usbÑ ¯disabledusb-phy@c5004000nvidia,tegra20-usb-phygÅ@@—ulpiv:]—regpll_uulpi-link}:„usbutmi-pads ¯disabledusb@c5008000nvidia,tegra20-ehciusb-ehcigÅ€@ ka—utmiv;};„usbѯokayusb-phy@c5008000nvidia,tegra20-usb-phygÅ€@Å@—utmi v;j—regpll_utimerutmi-pads};„usbutmi-padsÜ ö "8 J^¯okaysdhci@c8000000nvidia,tegra20-sdhcigÈ kv}„sdhci ¯disabledsdhci@c8000200nvidia,tegra20-sdhcigÈ kv } „sdhci ¯disabledsdhci@c8000400nvidia,tegra20-sdhcigÈ kvE}E„sdhci ¯disabledsdhci@c8000600nvidia,tegra20-sdhcigÈ kv}„sdhci¯okay : ™;¢cpuscpu@0[cpuarm,cortex-a9gcpu@1[cpuarm,cortex-a9gpmuarm,cortex-a9-pmuk89i2cmuxi2c-mux-pinctrl¬ ™ddcptaidle§·Ái2c@0gi2c@1gclocks simple-busclock@0 fixed-clockgX € regulators simple-busregulator@1regulator-fixedg àvdd_1v05 êËregulator@100regulator-fixedgdàvcc_24vn6n6ïregulator@101regulator-fixedgeàvdd_5v0ÞLK@LK@ï regulator@102regulator-fixedgfàvdd_3v3Þ2Z 2Z ïregulator@103regulator-fixedggàvdd_1v8Þw@w@ïsound4ad,tegra-audio-wm8903-tecnvidia,tegra-audio-wm8903éAvionic Design TEC{öHeadphone JackHPOUTRHeadphone JackHPOUTLInt SpkROPInt SpkRONInt SpkLOPInt SpkLONMic JackMICBIASIN1LMic Jack ! 4 I²vpq^—pll_apll_a_out0mclk #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathrtc0rtc1serial0device_typereginterruptsclocksresetsreset-namesrangesclock-namesnvidia,headstatusvdd-supplypll-supplynvidia,ddc-i2c-busnvidia,hpd-gpiointerrupt-controller#interrupt-cellsphandlearm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cells#gpio-cellsgpio-controllerpinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatedmasdma-namesreg-shift#pwm-cellsclock-frequencymicdet-cfgmicdet-delaygpio-cfgti,system-power-controllersys-supplyvin-sm0-supplyvin-sm1-supplyvin-sm2-supplyvinldo01-supplyvinldo23-supplyvinldo4-supplyvinldo678-supplyvinldo9-supplyregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltnvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,sys-clock-req-active-highreg-namesinterrupt-namesinterrupt-map-maskinterrupt-mapbus-rangeavdd-pex-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-clk-supplyassigned-addressesnvidia,num-lanesphy_typenvidia,has-legacy-modenvidia,needs-double-resetnvidia,phynvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,has-utmi-pad-registerscd-gpioswp-gpiosbus-widthi2c-parentpinctrl-1pinctrl-2enable-active-highvin-supplynvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,spkr-en-gpiosnvidia,hp-det-gpios