8(p-hardkernel,rk3326-odroid-go2rockchip,rk3326 +7ODROID-GO Advancealiases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000cpus+cpu@0cpuarm,cortex-a35psciZcpu@1cpuarm,cortex-a35psciZcpu@2cpuarm,cortex-a35psciZ cpu@3cpuarm,cortex-a35psciZ idle-statespscicpu-sleeparm,idle-state'8Ox`pcluster-sleeparm,idle-state'8O`pcpu0-opp-tableoperating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkin psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal/=O tripstrip-point-0_pkpassivetrip-point-1_Lkpassive soc-crit_8k criticalcooling-mapsmap0v  {map1v  {gpu-thermald/O xin24m fixed-clock n6xin24m]power-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+_power-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !power-domain@14I"syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+yio-domains$rockchip,px30-pmu-io-voltage-domainokay##reboot-modesyscon-reboot-modeRBRB RBRB RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart $$baudclkapb_pclk%%%*txrx4>Kdefault Y&'( disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk%%%*txrxKdefaultY)*+,cokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk%%%*txrxKdefaultY-./0c disabledinterrupt-controller@ff131000 arm,gic-400t@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+4io-domains rockchip,px30-io-voltage-domainokay121111lvdsrockchip,px30-lvds3dphy4 lvds disabledports+port@0+endpoint@05xserial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk%%%*txrx4>KdefaultY67okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk%%%*txrx4>KdefaultY8okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk%%%*txrx4>Kdefault Y9:; disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk%%% *txrx4>Kdefault Y<=> disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk%% % *txrx4>Kdefault Y?@A disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk KdefaultYB+okay*Bpmic@20rockchip,rk817  C KdefaultYDY rk808-clkout1xin32kgEsEEEEEEregulatorsDCDC_REG1 vdd_logic~0q#oregulator-state-mem5M~DCDC_REG2vdd_arm~pq#regulator-state-memiM~DCDC_REG3vcc_ddr#regulator-state-mem5DCDC_REG4vcc_3v32Z2Z#1regulator-state-memiM2ZLDO_REG2vcc_1v8w@w@#\regulator-state-mem5Mw@LDO_REG3vdd_1v0B@B@#regulator-state-mem5MB@LDO_REG4 vcc3v3_pmu2Z2Z##regulator-state-mem5M2ZLDO_REG5 vccio_sdw@2Z#2regulator-state-mem5M2ZLDO_REG6vcc_sd2Z2Z#hregulator-state-mem5M2ZLDO_REG7vcc_bl2Z2Zregulator-state-memiM2ZLDO_REG8vcc_lcd**sregulator-state-memiM*LDO_REG9vcc_cam--regulator-state-memiM-i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk KdefaultYF+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  KdefaultYG+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  KdefaultYH+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk%% % *txrxKdefaultYIJKL+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk%%%*txrxKdefaultYMNOPQ+ disabledwatchdog@ff1e0000 snps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYR disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYSokaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYT disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkKdefaultYU disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYV disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYW disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYX disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkKdefaultYY disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerbus simple-bus+dmac@ff240000arm,pl330arm,primecell$@ apb_pclk%tsadc@ff280000rockchip,px30-tsadc( $,P,Xtsadcapb_pclk tsadc-apb4KinitdefaultsleepYZ [Z okay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T6-Wsaradcapb_pclk saradc-apbokayH\nvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphyphy+id@7cpu-leakage@17performance@1eTclock-controller@ff2b0000rockchip,px30-cru+ ]$ xin24mgpll4 Y@@I Fq рр f@clock-controller@ff2bc000rockchip,px30-pmucru+]xin24m4 Y$$$ G$syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2-phy@100rockchip,px30-usb2phy $ phyclk f^ usb480m_phyokay^host-port} D linestateokayaotg-port}$BA@otg-bvalidotg-idlinestate disabled`phy@ff2e0000rockchip,px30-dsi-dphy.$ E refpclk>apb}_ okay3usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg@ ` usb2-phy_okayusb@ff340000 generic-ehci4 <ausb_ disabledusb@ff350000 generic-ohci5 =ausb_ disabledethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed4rmiiKdefaultYbc_ ^ stmmaceth disabledmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрKdefaultYdefg_okay  -C6CP]khw2mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрKdefault Yijk_  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрKdefault Ylmn_  disabledgpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI_okayodsi@ff450000rockchip,px30-mipi-dsiE KDpclk3dphy_ =apb4+okayports+port@0+endpoint@0pwport@1endpointqupanel@0elida,kd35t133rs tsportendpointuqvop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vop345 axiahbdclkv_ okayport+ endpoint@0wpendpoint@1x5iommu@ff460f00rockchip,iommuF M vopb_mmu aclkiface_ okayvqos@ff518000sysconQ qos@ff520000sysconR "qos@ff52c000sysconR qos@ff538000sysconS qos@ff538080sysconS qos@ff538100sysconS qos@ff538180sysconS qos@ff540000sysconT qos@ff540080sysconT qos@ff548000sysconT qos@ff548080sysconT qos@ff548100sysconT qos@ff548180sysconT  qos@ff548200sysconT !qos@ff550000sysconU qos@ff550080sysconU qos@ff550100sysconU qos@ff550180sysconU qos@ff558000sysconU qos@ff558080sysconU pinctrlrockchip,px30-pinctrl4y+gpio0@ff040000rockchip,gpio-bank $tCgpio1@ff250000rockchip,gpio-bank% \tgpio2@ff260000rockchip,gpio-bank& ]tgpio3@ff270000rockchip,gpio-bank' ^ttpcfg-pull-up|pcfg-pull-downpcfg-pull-none{pcfg-pull-none-2ma$pcfg-pull-up-2ma$pcfg-pull-up-4ma$}pcfg-pull-none-4ma$pcfg-pull-down-4ma$pcfg-pull-none-8ma$pcfg-pull-up-8ma$~pcfg-pull-none-12ma$ pcfg-pull-up-12ma$ pcfg-pull-none-smt3zpcfg-output-highHpcfg-output-lowTpcfg-input-high_pcfg-input_i2c0i2c0-xfer lz zBi2c1i2c1-xfer lzzFi2c2i2c2-xfer lzzGi2c3i2c3-xfer l z zHtsadctsadc-otp-pinl{Ztsadc-otp-outl{[uart0uart0-xfer l | |&uart0-ctsl {'uart0-rtsl {(uart1uart1-xfer l||6uart1-ctsl{7uart1-rtsl{uart2-m0uart2m0-xfer l||uart2-m1uart2m1-xfer l ||8uart3-m0uart3m0-xfer l||uart3m0-ctsl{uart3m0-rtsl{uart3-m1uart3m1-xfer l||9uart3m1-ctsl {:uart3m1-rtsl {;uart4uart4-xfer l||<uart4-ctsl{=uart4-rtsl{>uart5uart5-xfer l||?uart5-ctsl{@uart5-rtsl{Aspi0spi0-clkl}Ispi0-csnl}Jspi0-misol }Kspi0-mosil }Lspi0-clk-hsl~spi0-miso-hsl ~spi0-mosi-hsl ~spi1spi1-clkl}Mspi1-csn0l }Nspi1-csn1l }Ospi1-misol}Pspi1-mosil }Qspi1-clk-hsl~spi1-miso-hsl~spi1-mosi-hsl ~pdmpdm-clk0m0l{pdm-clk0m1l{pdm-clk1l{pdm-sdi0m0l{pdm-sdi0m1l{pdm-sdi1l{pdm-sdi2l{pdm-sdi3l{pdm-clk0m0-sleeplpdm-clk0m1-sleeplpdm-clk1-sleeplpdm-sdi0m0-sleeplpdm-sdi0m1-sleeplpdm-sdi1-sleeplpdm-sdi2-sleeplpdm-sdi3-sleepli2s0i2s0-8ch-mclkl{i2s0-8ch-sclktxl{i2s0-8ch-sclkrxl {i2s0-8ch-lrcktxl{i2s0-8ch-lrckrxl {i2s0-8ch-sdo0l{i2s0-8ch-sdo1l{i2s0-8ch-sdo2l{i2s0-8ch-sdo3l{i2s0-8ch-sdi0l{i2s0-8ch-sdi1l {i2s0-8ch-sdi2l {i2s0-8ch-sdi3l{i2s1i2s1-2ch-mclkl{i2s1-2ch-sclkl{)i2s1-2ch-lrckl{*i2s1-2ch-sdil{+i2s1-2ch-sdol{,i2s2i2s2-2ch-mclkl{i2s2-2ch-sclkl{-i2s2-2ch-lrckl{.i2s2-2ch-sdil{/i2s2-2ch-sdol{0sdmmcsdmmc-clkldsdmmc-cmdl~esdmmc-detl~fsdmmc-bus1l~sdmmc-bus4@l~~~~gsdiosdio-clkl{ksdio-cmdl|jsdio-bus4@l||||iemmcemmc-clkl lemmc-cmdl ~memmc-rstnoutl {emmc-bus1l~emmc-bus4@l~~~~emmc-bus8l~~~~~~~~nflashflash-cs0l{flash-rdyl {flash-dqsl {flash-alel {flash-clel {flash-wrnl {flash-csll{flash-rdnl{flash-bus8llcdclcdc-rgb-dclk-pinllcdc-rgb-m0-hsync-pinllcdc-rgb-m0-vsync-pinllcdc-rgb-m0-den-pinllcdc-rgb888-m0-data-pinsl     lcdc-rgb666-m0-data-pins l     lcdc-rgb565-m0-data-pinsl     lcdc-rgb888-m1-data-pinsl   lcdc-rgb666-m1-data-pinsl   lcdc-rgb565-m1-data-pinsl   pwm0pwm0-pinl{Rpwm1pwm1-pinl{Spwm2pwm2-pinl {Tpwm3pwm3-pinl{Upwm4pwm4-pinl{Vpwm5pwm5-pinl{Wpwm6pwm6-pinl{Xpwm7pwm7-pinl{Ygmacrmii-pinsl{{{{{ {bmac-refclk-12mal cmac-refclkl {cif-m0cif-clkout-m0l {dvp-d2d9-m0l{{{{{{{{{ { { {dvp-d0d1-m0 l {{d10-d11-m0 l{{cif-m1cif-clkout-m1l{dvp-d2d9-m1l{{{{ { {{{{{{{dvp-d0d1-m1 l{{d10-d11-m1 l{{ispisp-prelightl{btnsbtn-pinsl|||| | |||||||||||headphonehp-detlledsblue-led-pinl{pmicdc-detl {pmic-intl |Dsoc_slppin_gpiolsoc_slppin_rstl{soc_slppin_slpl{chosenzserial2:115200n8backlightpwm-backlightargpio-keys gpio-keysKdefaultYsw1 0 DPAD-UP sw2 0  DPAD-DOWN!sw3 0 DPAD-LEFT"sw4 0 DPAD-RIGHT#sw5 0BTN-A1sw6 0BTN-B0sw7 0BTN-Y4sw8 0BTN-X3sw9 0F1sw10 0F2sw11 0F3sw12 0F4sw13 0F5sw14 0F6sw15 0 TOP-LEFT6sw16 0 TOP-RIGHT7gpio-leds gpio-ledsKdefaultYled-0blue:heartbeat 0C heartbeatvccsysregulator-fixed vcc3v8_sys99Evcc_hostregulator-fixed vcc_hostLK@LK@ CE compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointi2c-scl-falling-time-nsi2c-scl-rising-time-nswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendnum-cs#pwm-cellsrangesarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modebus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delaycd-gpiossd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymali-supplybacklightiovcc-supplyreset-gpiosvdd-supplyiommus#iommu-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathpower-supplypwmslabellinux,codelinux,default-triggergpioenable-active-highvin-supply