8(  rockchip,px30-evbrockchip,px30 +7Rockchip PX30 EVBaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000cpus+cpu@0cpuarm,cortex-a35psciZcpu@1cpuarm,cortex-a35psciZcpu@2cpuarm,cortex-a35psciZ cpu@3cpuarm,cortex-a35psciZ idle-statespscicpu-sleeparm,idle-state'8Ox`pcluster-sleeparm,idle-state'8O`pcpu0-opp-tableoperating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkin psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal/=O tripstrip-point-0_pkpassivetrip-point-1_Lkpassivesoc-crit_8k criticalcooling-mapsmap0v {map1v {gpu-thermald/O xin24m fixed-clock n6xin24mapower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+cpower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"power-domain@14I#syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+io-domains$rockchip,px30-pmu-io-voltage-domainokay$$reboot-modesyscon-reboot-modeRBRB RBRB RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart %%baudclkapb_pclk%&&*txrx4>Kdefault Y'() disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk%&&*txrxKdefaultY*+,-cokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk%&&*txrxKdefaultY./01c disabledinterrupt-controller@ff131000 arm,gic-400t@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+6io-domains rockchip,px30-io-voltage-domainokay234$42lvdsrockchip,px30-lvds5dphy6 lvds disabledports+port@0+endpoint@07~endpoint@18serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk%&&*txrx4>KdefaultY9:okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk%&&*txrx4>KdefaultY; disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk%&&*txrx4>Kdefault Y<=> disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk%&& *txrx4>Kdefault Y?@A disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk%& & *txrx4>Kdefault YBCDokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk KdefaultYE+okaypmic@20rockchip,rk809  FKdefaultYG*K xin32kYHeHqH}HIIIIHregulatorsDCDC_REG1vdd_log~pq-vregulator-state-mem?W~DCDC_REG2vdd_arm~pq-regulator-state-memsW~DCDC_REG3vcc_ddr-regulator-state-mem?DCDC_REG4vcc_3v0---4regulator-state-mem?W-DCDC_REG5 vcc3v3_sys2Z2Z-Iregulator-state-mem?W2ZLDO_REG1vcc_1v0B@B@-regulator-state-mem?WB@LDO_REG2vcc_1v8w@w@-2regulator-state-mem?Ww@LDO_REG3vdd_1v0B@B@-regulator-state-mem?WB@LDO_REG4 vcc3v0_pmu---$regulator-state-mem?W-LDO_REG5 vccio_sdw@2Z-3regulator-state-mem?W2ZLDO_REG6vcc_sd2Z2Z-mregulator-state-mem?W2ZLDO_REG7 vcc2v8_dvp**-regulator-state-memsW*LDO_REG8 vcc1v8_dvpw@w@-regulator-state-mem?Ww@LDO_REG9 vcc1v5_dvp``-regulator-state-memsW`SWITCH_REG1 vcc3v3_lcd-KSWITCH_REG2 vcc5v0_host-i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk KdefaultYJ+okaysensor@dasahi-kasei,ak8963  F$100010001touchscreen@14goodix,gt1151 F F F Ksensor@4c fsl,mma7660L Fi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  KdefaultYL+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  KdefaultYM+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk%& & *txrxKdefaultYNOPQ+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk%&&*txrxKdefaultYRSTUV+ disabledwatchdog@ff1e0000 snps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYW disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYXokaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYY disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkKdefaultYZ disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultY[ disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultY\ disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultY] disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkKdefaultY^ disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerbus simple-bus+dmac@ff240000arm,pl330arm,primecell$@ apb_pclk&tsadc@ff280000rockchip,px30-tsadc( $,P,Xtsadcapb_pclk- 4tsadc-apb6@KinitdefaultsleepY_W`a_kokay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wsaradcapb_pclk- 4saradc-apbokay2nvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphy-4phy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ a% xin24mgpll6 8@IFq рр clock-controller@ff2bc000rockchip,px30-pmucru+axin24m6 %%% G%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2-phy@100rockchip,px30-usb2phy % phyclk b usb480m_phyokaybhost-port D linestateokayeotg-port$BA@otg-bvalidotg-idlinestateokaydphy@ff2e0000rockchip,px30-dsi-dphy.% E refpclk->4apbc okay5usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otg#otg+=L@ d usb2-phycokayusb@ff340000 generic-ehci4 <eusbcokayusb@ff350000 generic-ohci5 =eusbcokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed6[rmiiKdefaultYfgc -^ 4stmmacethokaydoutputq4 |h  PPmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрKdefaultYijklcokay )6DmP3mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрKdefault Ynopc okay]sq6mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрKdefault Yrstc okaysuD4P2gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIcokayvdsi@ff450000rockchip,px30-mipi-dsiE KDpclk5dphyc -=4apb6+okayports+port@0+endpoint@0w}endpoint@1xport@1endpointy{panel@0xinpeng,xpp055c272z2Kportendpoint{yvop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vop-345 4axiahbdclk|c okayport+ endpoint@0}wendpoint@1~7iommu@ff460f00rockchip,iommuF M vopb_mmu aclkifacec okay|vop@ff470000rockchip,px30-vop-litG Naclk_vopdclk_vophclk_vop-789 4axiahbdclkc okayport+ endpoint@0xendpoint@18iommu@ff470f00rockchip,iommuG N vopl_mmu aclkifacec okayqos@ff518000sysconQ qos@ff520000sysconR #qos@ff52c000sysconR qos@ff538000sysconS qos@ff538080sysconS qos@ff538100sysconS qos@ff538180sysconS qos@ff540000sysconT qos@ff540080sysconT qos@ff548000sysconT qos@ff548080sysconT qos@ff548100sysconT  qos@ff548180sysconT !qos@ff548200sysconT "qos@ff550000sysconU qos@ff550080sysconU qos@ff550100sysconU qos@ff550180sysconU qos@ff558000sysconU qos@ff558080sysconU pinctrlrockchip,px30-pinctrl6+gpio0@ff040000rockchip,gpio-bank %tFgpio1@ff250000rockchip,gpio-bank% \tgpio2@ff260000rockchip,gpio-bank& ]thgpio3@ff270000rockchip,gpio-bank' ^tpcfg-pull-up pcfg-pull-down pcfg-pull-none "pcfg-pull-none-2ma " /pcfg-pull-up-2ma  /pcfg-pull-up-4ma  /pcfg-pull-none-4ma " /pcfg-pull-down-4ma  /pcfg-pull-none-8ma " /pcfg-pull-up-8ma  /pcfg-pull-none-12ma " / pcfg-pull-up-12ma  / pcfg-pull-none-smt " >pcfg-output-high Spcfg-output-low _pcfg-input-high  jpcfg-input ji2c0i2c0-xfer w Ei2c1i2c1-xfer wJi2c2i2c2-xfer wLi2c3i2c3-xfer w  Mtsadctsadc-otp-pin w_tsadc-otp-out w`uart0uart0-xfer w  'uart0-cts w (uart0-rts w )uart1uart1-xfer w9uart1-cts w:uart1-rts wuart2-m0uart2m0-xfer w;uart2-m1uart2m1-xfer w uart3-m0uart3m0-xfer wuart3m0-cts wuart3m0-rts wuart3-m1uart3m1-xfer w<uart3m1-cts w =uart3m1-rts w >uart4uart4-xfer w?uart4-cts w@uart4-rts wAuart5uart5-xfer wBuart5-cts wCuart5-rts wDspi0spi0-clk wNspi0-csn wOspi0-miso w Pspi0-mosi w Qspi0-clk-hs wspi0-miso-hs w spi0-mosi-hs w spi1spi1-clk wRspi1-csn0 w Sspi1-csn1 w Tspi1-miso wUspi1-mosi w Vspi1-clk-hs wspi1-miso-hs wspi1-mosi-hs w pdmpdm-clk0m0 wpdm-clk0m1 wpdm-clk1 wpdm-sdi0m0 wpdm-sdi0m1 wpdm-sdi1 wpdm-sdi2 wpdm-sdi3 wpdm-clk0m0-sleep wpdm-clk0m1-sleep wpdm-clk1-sleep wpdm-sdi0m0-sleep wpdm-sdi0m1-sleep wpdm-sdi1-sleep wpdm-sdi2-sleep wpdm-sdi3-sleep wi2s0i2s0-8ch-mclk wi2s0-8ch-sclktx wi2s0-8ch-sclkrx w i2s0-8ch-lrcktx wi2s0-8ch-lrckrx w i2s0-8ch-sdo0 wi2s0-8ch-sdo1 wi2s0-8ch-sdo2 wi2s0-8ch-sdo3 wi2s0-8ch-sdi0 wi2s0-8ch-sdi1 w i2s0-8ch-sdi2 w i2s0-8ch-sdi3 wi2s1i2s1-2ch-mclk wi2s1-2ch-sclk w*i2s1-2ch-lrck w+i2s1-2ch-sdi w,i2s1-2ch-sdo w-i2s2i2s2-2ch-mclk wi2s2-2ch-sclk w.i2s2-2ch-lrck w/i2s2-2ch-sdi w0i2s2-2ch-sdo w1sdmmcsdmmc-clk wisdmmc-cmd wjsdmmc-det wksdmmc-bus1 wsdmmc-bus4@ wlsdiosdio-clk wpsdio-cmd wosdio-bus4@ wnemmcemmc-clk w remmc-cmd w semmc-rstnout w emmc-bus1 wemmc-bus4@ wemmc-bus8 wtemmc-reset w flashflash-cs0 wflash-rdy w flash-dqs w flash-ale w flash-cle w flash-wrn w flash-csl wflash-rdn wflash-bus8 wlcdclcdc-rgb-dclk-pin wlcdc-rgb-m0-hsync-pin wlcdc-rgb-m0-vsync-pin wlcdc-rgb-m0-den-pin wlcdc-rgb888-m0-data-pins w     lcdc-rgb666-m0-data-pins w     lcdc-rgb565-m0-data-pins w     lcdc-rgb888-m1-data-pins w   lcdc-rgb666-m1-data-pins w   lcdc-rgb565-m1-data-pins w   pwm0pwm0-pin wWpwm1pwm1-pin wXpwm2pwm2-pin w Ypwm3pwm3-pin wZpwm4pwm4-pin w[pwm5pwm5-pin w\pwm6pwm6-pin w]pwm7pwm7-pin w^gmacrmii-pins w fmac-refclk-12ma w gmac-refclk w cif-m0cif-clkout-m0 w dvp-d2d9-m0 w   dvp-d0d1-m0 w d10-d11-m0 wcif-m1cif-clkout-m1 wdvp-d2d9-m1 w  dvp-d0d1-m1 wd10-d11-m1 wispisp-prelight wheadphonehp-det wpmicpmic_int wGsoc_slppin_gpio wsoc_slppin_slp wsoc_slppin_rst wsdio-pwrseqwifi-enable-h wchosen serial5:115200n8adc-keys adc-keys  buttons w@ desc-key esc  0home-key home f menu-key menu  xvol-down-key volume down r vol-up-key volume up s Bhbacklightpwm-backlight a Kzemmc-pwrseqmmc-pwrseq-emmcYKdefault  usdio-pwrseqmmc-pwrseq-simpleKdefaultY Fqvccsysregulator-fixed vcc5v0_sys-LK@LK@H compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendgpiosvdd-supplymount-matrixirq-gpiosreset-gpiosVDDIO-supplynum-cs#pwm-cellsrangesarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplybacklightiovcc-supplyvci-supplyiommus#iommu-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpwmspower-supply