8(tHEengicam,icore-stm32mp1-edimm2.2engicam,icore-stm32mp1st,stm32mp157-&Engicam i.Core STM32MP1 EDIMM2.2 Starter Kitcpuscpu@0arm,cortex-a7,&6Hrxtx disabledaudio-controller@4000c000st,stm32h7-i2sH@ T3 C=>Hrxtx disabledaudio-controller@4000d000st,stm32h7-spdifrxH@07kclk Ta C]^ Hrxrx-ctrl disabledserial@4000e000st,stm32h7-uartH@ ]0q C+,Hrxtx disabledserial@4000f000st,stm32h7-uartH@ ]0q C-.Hrxtx disabledserial@40010000st,stm32h7-uartH@ ]0qokaydefaultsleepidle   serial@40011000st,stm32h7-uartH@ ]0q CABHrxtx disabledi2c@40012000st,stm32mp15-i2cH@   eventerrorT 0L q disabledi2c@40013000st,stm32mp15-i2cH@0  eventerrorT!"0L qokaydefaultsleep  i2c@40014000st,stm32mp15-i2cH@@  eventerrorTHI0L q disabledi2c@40015000st,stm32mp15-i2cH@P  eventerrorTkl0L q disabledcec@40016000 st,stm32-cecH@` T^0 7cechdmi-cec disableddac@40017000st,stm32h7-dac-coreH@p07pclk disableddac@1 st,stm32-dacH disableddac@2 st,stm32-dacH disabledserial@40018000st,stm32h7-uartH@ ] 0q COPHrxtx disabledserial@40019000st,stm32h7-uartH@ ]!0q CQRHrxtx disabledtimer@44000000st,stm32-timersHD0T brkuptrg-comcc07intpC   Hch1ch2ch3ch4uptrigcom disabledpwm st,stm32-pwmR disabledtimer@0st,stm32h7-timer-triggerH disabledcounterst,stm32-timer-counter disabledtimer@44001000st,stm32-timersHD0T+,-. brkuptrg-comcc07intpC/012345Hch1ch2ch3ch4uptrigcom disabledpwm st,stm32-pwmR disabledtimer@7st,stm32h7-timer-triggerH disabledcounterst,stm32-timer-counter disabledserial@44003000st,stm32h7-uartHD0 ]0q CGHHrxtx disabledspi@44004000st,stm32h7-spiHD@ T#0LH C%&Hrxtx disabledaudio-controller@44004000st,stm32h7-i2sHD@ T# C%&Hrxtx disabledspi@44005000st,stm32h7-spiHDP TT0LI CSTHrxtx disabledtimer@44006000st,stm32-timersHD` Tt global07int@CijklHch1uptrigcom disabledpwm st,stm32-pwmR disabledtimer@14st,stm32h7-timer-triggerH disabledtimer@44007000st,stm32-timersHDp Tu global07int CmnHch1up disabledpwm st,stm32-pwmR disabledtimer@15st,stm32h7-timer-triggerH disabledtimer@44008000st,stm32-timersHD Tv global07int CopHch1up disabledpwm st,stm32-pwmR disabledtimer@16st,stm32h7-timer-triggerH disabledspi@44009000st,stm32h7-spiHD TU0LJ CUVHrxtx disabledsai@4400a000st,stm32h7-sai DHDD TWLP disabledaudio-controller@4400a004st,stm32-sai-sub-aH 07sai_ckCW disabledaudio-controller@4400a024st,stm32-sai-sub-bH$ 07sai_ckCX disabledsai@4400b000st,stm32h7-sai DHDD T[LQ disabledaudio-controller@4400b004st,stm32-sai-sub-aH 07sai_ckCY disabledaudio-controller@4400b024st,stm32-sai-sub-bH$ 07sai_ckCZ disabledsai@4400c000st,stm32h7-sai DHDD TrLR disabledaudio-controller@4400c004st,stm32-sai-sub-aH 07sai_ckCq disabledaudio-controller@4400c024st,stm32-sai-sub-bH$ 07sai_ckCr disableddfsdm@4400d000st,stm32mp1-dfsdmHD07dfsdm disabledfilter@0st,stm32-dfsdm-adcH TnCeHrx disabledfilter@1st,stm32-dfsdm-adcH ToCfHrx disabledfilter@2st,stm32-dfsdm-adcH TpCgHrx disabledfilter@3st,stm32-dfsdm-adcH TqChHrx disabledfilter@4st,stm32-dfsdm-adcH TsC[Hrx disabledfilter@5st,stm32-dfsdm-adcH T~C\Hrx disableddma-controller@48000000 st,stm32-dmaHH`T   /0GL$/:Ldma-controller@48001000 st,stm32-dmaHH`T89:;<DEF0HL$/:Ldma-router@48002000st,stm32h7-dmamuxHH @$:GS0ILLadc@48003000st,stm32mp1-adc-coreHH0TZ0J7busadc disabledLadc@0st,stm32mp1-adcHrTC Hrx disabledadc@100st,stm32mp1-adcHrTC Hrx`lvrefint disabledchannel@13H }vrefintchannel@14H}vddcoremmc@48004000(st,stm32-sdmmc2arm,pl18xarm,primecell%1HH@ T0x 7apb_pclkL' disabledusb-otg@49000000st,stm32mp15-hsotgsnps,dwc2HI 0 7otgutmiLdwc2 Tb  otg disabledmailbox@4c001000st,stm32mp1-ipcc%HL1]=e rxtx0SqokayL1dcmi@4c006000st,stm32-dcmiHL` TNM0M7mclkCKHtx disabledrcc@50000000st,stm32mp1-rccsysconHP<Lpwr@50001000st,stm32mp1,pwr-regHPreg11Ireg11XpLreg18Ireg18Xw@pw@Lusb33Iusb33X2Zp2ZLpwr_mcu@50001014st,stm32mp151-pwr-mcusysconHPL)interrupt-controller@5000d000st,stm32mp1-extisysconHPLsyscon@50020000st,stm32mp157-syscfgsysconHP03Ltimer@50021000st,stm32-lptimerHP ]007muxq disabledpwmst,stm32-pwm-lpR disabledtrigger@1st,stm32-lptimer-triggerH disabledcounterst,stm32-lptimer-counter disabledtimer@50022000st,stm32-lptimerHP  ]207muxq disabledpwmst,stm32-pwm-lpR disabledtrigger@2st,stm32-lptimer-triggerH disabledtimer@50023000st,stm32-lptimerHP0 ]407muxq disabledpwmst,stm32-pwm-lpR disabledtimer@50024000st,stm32-lptimerHP@ ]507muxq disabledpwmst,stm32-pwm-lpR disabledvrefbuf@50025000st,stm32-vrefbufHPPX&%p&%04okaysai@50027000st,stm32h7-sai PpHPpPs TL disabledaudio-controller@50027004st,stm32-sai-sub-aH 07sai_ckCc disabledaudio-controller@50027024st,stm32-sai-sub-bH$ 07sai_ckCd disabledthermal@50028000st,stm32-thermalHP T057pclkokayLhash@54002000st,stm32f756-hashHT  TP0a C Hin disabledrng@54003000 st,stm32-rngHT00| okaydma-controller@58000000st,stm32h7-mdmaHX Tz0d $S :0Lmemory-controller@58002000st,stm32mp1-fmc2-ebiHX 0y  disabledP`dhlnand-controller@4,0st,stm32mp1-fmc2-nfcHH   T0HC    Htxrxecc disabledspi@58003000st,stm32f469-qspiHX0p qspiqspi_mm T\0CHtxrx0z  disabledmmc@58005000(st,stm32-sdmmc2arm,pl18xarm,primecell%1HXP T10v 7apb_pclk 'okaydefaultopendrainsleepmmc@58007000(st,stm32-sdmmc2arm,pl18xarm,primecell%1HXp T|0w 7apb_pclk ' disabledcrc@58009000st,stm32f7-crcHX0n disabledethernet@5800a000#st,stm32mp1-dwmacsnps,dwmac-4.20aHX  stmmaceth]= macirq67stmmacethmac-clk-txmac-clk-rxeth-ckptp_refethstp00igh{p -= disabledstmmac-axi-configFVfLusb@5800c000 generic-ohciHX 0o  TJ disabledLusb@5800d000 generic-ehciHX 0o  TKp disableddisplay-controller@5a001000st,stm32-ltdcHZTXY07lcd okayportendpointzL'watchdog@5a002000st,stm32mp1-iwdgHZ 0: 7pclklsiokay usbphyc@5a006000st,stm32mp1-usbphycHZ`0  disabledLusb-phy@0Husb-phy@1Hserial@5c000000st,stm32h7-uartH\ ]0q disabledspi@5c001000st,stm32h7-spiH\ TV0 @0C"#Hrxtx disabledi2c@5c002000st,stm32mp15-i2cH\   eventerrorT_`0 B q disabledrtc@5c004000st,stm32mp1-rtcH\@0A 7pclkrtc_ck ]okayefuse@5c005000st,stm32mp15-bsecH\Ppart-number-otp@4Hvrefin-cal@52HRLcalib@5cH\calib@5eH^i2c@5c009000st,stm32mp15-i2cH\  eventerrorT0 C  qokaydefaultsleep bridge@2c ti,sn65dsi84H, !portsport@0Hendpointz"L(port@2Hendpointz#L4tamp@5c00a000 st,stm32-tampsysconsimple-mfdH\L*pinctrl@50002000st,stm32mp157-pinctrl P r `L$gpio@50002000H0TGPIOAokay $gpio@50003000H0UGPIOBokay $gpio@50004000H 0VGPIOCokay $ gpio@50005000H00WGPIODokay $0L2gpio@50006000H@0XGPIOEokay $@gpio@50007000HP0YGPIOFokay $PL!gpio@50008000H`0ZGPIOGokay $`gpio@50009000Hp0[GPIOHokay $pgpio@5000a000H0\GPIOIokay $gpio@5000b000H0]GPIOJokay $gpio@5000c000H0^GPIOKokay $adc1-ain-0pins[ #adc1-in6-0pins\adc12-ain-0pins#\]^adc12-ain-1pins\]adc12-usb-cc-pins-0pinscec-0pins%2Ccec-sleep-0pinscec-1pins%2Ccec-sleep-1pinsdac-ch1-0pinsdac-ch2-0pinsdcmi-0pins<xyz{|~Fw%dcmi-sleep-0pins<xyz{|~Fwdcmi-1pins,&z{AK3M%dcmi-sleep-1pins,&z{AK3Mdcmi-2pins4 z@A~FwMdcmi-sleep-2pins4 z@A~Fwrgmii-0pins1 e d m n " B  ! %ZCpins2 %ZCpins3$ %     %rgmii-sleep-0pins1<edmn"B!$%rgmii-1pins1 e d m n " B  ! %ZCpins2 %ZCpins3$ % v w   %rgmii-sleep-1pins1<edmn"B!$%vwrgmii-2pins1 e d  n " B k ! %ZCpins2 %ZCpins3$ % v    %rgmii-sleep-2pins1<edn"Bk!$%vrgmii-3pins1e m n " B  ! %ZCpins2 %ZCpins3$ % v    %rgmii-sleep-3pins1<edmn"B!$%vrgmii-4pins1d m n " B  %ZCpins2$ % v w   %rgmii-sleep-4pins10dmn"B$%vwrmii-0pins1m n   ! %ZCpins2 $ %  %rmii-sleep-0pins1$mn!$%rmii-1pins1! m n %ZCpins2 %ZCpins3  $ % %pins4 rmii-sleep-1pins1$!$%mnrmii-2pins1m n    ! %ZCpins2 $ %  %rmii-sleep-2pins1$mn!$%fmc-0pins144 5 ; < > ? 0 1 G H I J i %ZCpins26 Mfmc-sleep-0pins845;<>?01GHIJ6ifmc-1pinsT4 5  > ? 0 1 G H I J K L M N O 8 9 : i l %ZCfmc-sleep-1pinsT45>?01GHIJKLMNO89:ili2c1-0pins<_%2Ci2c1-sleep-0pins<_i2c1-1pins^_%2Ci2c1-sleep-1pins^_i2c2-0L pinstu%2Ci2c2-sleep-0L pinstui2c2-1pinsu%2Ci2c2-sleep-1pinsui2c2-2pinsQu%2Ci2c2-sleep-2pinsQui2c5-0pins  %2Ci2c5-sleep-0pins  i2c5-1pins01%2Ci2c5-sleep-1pins01i2s2-0pins  CZ%i2s2-sleep-0pins  ltdc-0pinspgZrsxyz |OEF}~9lj:8%ZCltdc-sleep-0pinspgZrsxyz |OEF}~9lj:8ltdc-1pinsp%ZCltdc-sleep-1pinspltdc-2pins1T  36:KLMOt xyz}%ZCpins2N%ZCltdc-sleep-2pins1X 36:KLMOtxyz}Nltdc-3pins1g%ZCpins2lMmsxy{|OE}Kt h9lj:L%ZCltdc-sleep-3pinspgMmsxy{|OE}Kth9lj:Lmco1-0pins %ZCmco1-sleep-0pins mco2-0pinsb%ZCmco2-sleep-0pinsbm-can1-0pins1} CZ%pins2 %m_can1-sleep-0pins}m-can1-1pins1 CZ%pins2 %m_can1-sleep-1pins  m-can1-2pins1} CZ%pins2~ %m_can1-sleep-2pins}~m-can2-0pins1 CZ%pins2 %m_can2-sleep-0pinspwm1-0pins IKNjZCpwm1-sleep-0pins IKNpwm1-1pinsIjZCpwm1-sleep-1pinsIpwm1-2pinsKZCpwm1-sleep-2pinsKpwm2-0pinsjZCpwm2-sleep-0pinspwm3-0pins'jZCpwm3-sleep-0pins'pwm3-1pins%ZCpwm3-sleep-1pinspwm4-0pins>?jZCpwm4-sleep-0pins>?pwm4-1pins=jZCpwm4-sleep-1pins=pwm5-0pins{jZCpwm5-sleep-0pins{pwm5-1pins {|%ZCpwm5-sleep-1pins {|pwm8-0pinsjZCpwm8-sleep-0pinspwm8-1pins)ZCpwm8-sleep-1pins)pwm12-0pinsvjZCpwm12-sleep-0pinsvqspi-clk-0pinsZ %ZCqspi-clk-sleep-0pinsZqspi-bk1-0pinsX Y W V %ZCqspi-bk1-sleep-0pinsXYWVqspi-bk2-0pinsr s j g %ZCqspi-bk2-sleep-0pinsrsjgqspi-cs1-0pins MZCqspi-cs1-sleep-0pinsqspi-cs2-0pins MZCqspi-cs2-sleep-0pins sai2a-0pins @ CZ%sai2a-sleep-0pins@sai2a-1pins1  = CZ%sai2a-sleep-1pins =sai2a-2pins = ; < CZ%sai2a-sleep-2pins =;<sai2b-0pins1 L M N CZ%pins2[ %sai2b-sleep-0pins[LMNsai2b-1pins[ %sai2b-sleep-1pins[sai2b-2pins1[ %sai2b-sleep-2pins[sai2b-3pins1 r s CZ%pins2[ %sai2b-sleep-3pins1r s[sai4a-0pins CZ%sai4a-sleep-0pinssdmmc1-b4-0Lpins1( ) * + 2 CZ%pins2, CZ%sdmmc1-b4-od-0Lpins1( ) * + CZ%pins2, CZ%pins32 C2%sdmmc1-b4-init-0pins1( ) * + CZ%sdmmc1-b4-sleep-0Lpins()*+,2sdmmc1-b4-1pins1( ) F + 2 CZ%pins2, CZ%sdmmc1-b4-od-1pins1( ) F + CZ%pins2, CZ%pins32 C2%sdmmc1-b4-sleep-1pins()F+,2sdmmc1-dir-0pins1 R '  CZMpins2D Msdmmc1-dir-init-0pins1 R '  CZMsdmmc1-dir-sleep-0pinsR'Dsdmmc1-dir-1pins1 R N  CZMpins2D Msdmmc1-dir-sleep-1pinsRNDsdmmc2-b4-0pins1    f CZMpins2C CZMsdmmc2-b4-od-0pins1    CZMpins2C CZMpins3f C2Msdmmc2-b4-sleep-0pinsCfsdmmc2-b4-1pins1    f CZ%pins2C CZ%sdmmc2-b4-od-1pins1    CZ%pins2C CZ%pins3f C2%sdmmc2-d47-0pins E 3 CZMsdmmc2-d47-sleep-0pins E3sdmmc2-d47-1pins & ' CZ%sdmmc2-d47-sleep-1pins &'sdmmc2-d47-2pins  & ' CZMsdmmc2-d47-sleep-2pins&'sdmmc2-d47-3pins E ' sdmmc2-d47-sleep-3pins E'sdmmc2-d47-4pins & 3 CZMsdmmc2-d47-sleep-4pins &3sdmmc3-b4-0pins1P T U 7 Q CZMpins2o CZMsdmmc3-b4-od-0pins1P T U 7 CZMpins2o CZMpins3Q C2Msdmmc3-b4-sleep-0pinsPTU7oQsdmmc3-b4-1pins1P T 5 7 0 CZMpins2o CZMsdmmc3-b4-od-1pins1P T 5 7 CZMpins2o CZMpins30 C2Msdmmc3-b4-sleep-1pinsPT57o0spdifrx-0pinsl %spdifrx-sleep-0pinslspi1-1pins1%ZCpins2%spi2-0pins1%ZCpins2%spi2-1pins1%ZCpins2%spi2-2pins1%Zpins2jspi4-0pinsLF%ZCpins2M%spi5-0pins1WY%ZCpins2X%stusb1600-0pinsMuart4-0L pins1k%ZCpins2 %uart4-idle-0L pins1kpins2 %uart4-sleep-0L pinskuart4-1pins11 %ZCpins2 %uart4-2pins1k%ZCpins2 %uart4-3pins1 %ZCpins2 %uart4-idle-3pins1 pins2 %uart4-sleep-3pins uart5-0pins1%ZCpins2 %uart7-0pins1H%ZCpins2 GJI%uart7-1pins1W%ZCpins2V%uart7-2pins1H%ZCpins2GMuart7-idle-2pins1Hpins2GMuart7-sleep-2pinsHGuart8-0pins1A %ZCpins2@ %uart8rtscts-0pinsg j %usart1-0pins1 %ZCpins2 %usart1-idle-0pins1  usart1-sleep-0pins  usart2-0pins1U4%ZCpins263%usart2-sleep-0pinsU463usart2-1pins1U%ZCpins2TO%usart2-sleep-1pinsUTOusart2-2pins154%ZCpins263%usart2-idle-2pins153pins24%ZCpins36%usart2-sleep-2pins5463usart3-0pins1%ZCpins2 %usart3-idle-0pins1pins2 %usart3-sleep-0pinsusart3-1pins1h %ZCpins2 Musart3-idle-1pins1pins2h %ZCpins3 Musart3-sleep-1pinshusart3-2pins1h %ZCpins2 Musart3-idle-2pins1pins2h %ZCpins3 Musart3-sleep-2pinshusart3-3pins1h %ZCpins29;%usart3-idle-3pins1 h;pins29%usart3-sleep-3pinsh;9usart3-4pins1h %ZCpins2;Musart3-idle-4pins1;pins2h %ZCpins3Musart3-sleep-4pinsh;usart3-5pins1<%ZCpins2 ;%usbotg-hs-0pins usbotg-fs-dp-dm-0pins  pinctrl@54004000st,stm32mp157-z-pinctrl T@r `L%gpio@54004000H0_GPIOZy okay %i2c2-0pins%2Ci2c2-sleep-0pinsi2c4-0pins%2Ci2c4-sleep-0pinsi2c6-0Lpins%2Ci2c6-sleep-0L pinsspi1-0pins1%ZCpins2%spi1-sleep-0pins usart1-1pins1%ZCpins2%usart1-idle-1pins1pins2%usart1-sleep-1pinscan@4400e000 bosch,m_canHDDm_canmessage_ramT  int0int10 7hclkcclk   disabledcan@4400f000 bosch,m_canHDD(m_canmessage_ramT  int0int10 7hclkcclk   disabledgpu@59000000 vivante,gcHY Tm0e~ 7buscore dsi@5a000000 st,stm32-dsiHZ0&7pclkrefpx_clk apbokayportsport@0Hendpointz'Lport@1Hendpointz(L"ahbst,mlahbsimple-bus$800m4@10000000st,stm32mp1-m4H08 !mcu_rst   ) *D *Hokay+,-./0111 vq0vq1shutdownrTDmemory@c0000000/soc/serial@40010000chosenFserial0:115200n8backlightgpio-backlight 2 RL3panel'yes-optoelectronics,ytc700tlag-05-201c]3gportendpointz4L# #address-cells#size-cellscompatiblemodelclock-frequencydevice_typeregphandleinterruptsinterrupt-affinityinterrupt-parentmethod#interrupt-cellsinterrupt-controller#clock-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisst,syscfgstatusrangesinterrupt-namesclocksclock-namesdmasdma-names#pwm-cellsinterrupts-extendedwakeup-sourceresets#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pinctrl-2st,syscfg-fmpi2c-analog-filteri2c-scl-falling-time-nsi2c-scl-rising-time-ns#io-channel-cells#dma-cellsst,mem2memdma-requestsdma-mastersdma-channelsnvmem-cellsnvmem-cell-nameslabelarm,primecell-periphidcap-sd-highspeedcap-mmc-highspeedmax-frequencyreset-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeotg-revusb33d-supply#mbox-cellsst,proc-id#reset-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltvdda-supply#thermal-sensor-cellsdma-maxburstreg-namesbus-widthdisable-wpst,neg-edgevmmc-supplyst,sysconsnps,mixed-burstsnps,pblsnps,en-tx-lpi-clockgatingsnps,axi-configsnps,tsosnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blencompanionremote-endpointtimeout-secvdda1v1-supplyvdda1v8-supply#phy-cellsenable-gpiosdata-lanesst,packagegpio-controller#gpio-cellsst,bank-namengpiosgpio-rangespinmuxbias-disabledrive-open-drainslew-ratebias-pull-updrive-push-pullbias-pull-downst,bank-ioportbosch,mram-cfgphy-dsi-supplydma-rangesst,syscfg-holdbootst,syscfg-pddsst,syscfg-rsc-tblst,syscfg-m4-statememory-regionmboxesmbox-namesno-mapregulator-always-onvin-supplyserial0stdout-pathdefault-onbacklightpower-supply