U8d(,+DH electronics STM32MP151A DHCOR TestbenchF!dh,stm32mp151a-dhcor-testbenchdh,stm32mp151a-dhcor-somst,stm32mp151cpuscpu@0!arm,cortex-a7,&6Hrxtx disabledaudio-controller@4000c000!st,stm32h7-i2sH@ T3 C=>Hrxtx disabledaudio-controller@4000d000!st,stm32h7-spdifrxH@07kclk Ta C]^ Hrxrx-ctrl disabledserial@4000e000!st,stm32h7-uartH@ ]0q C+,Hrxtx disabledserial@4000f000!st,stm32h7-uartH@ ]0q C-.Hrxtx disabledserial@40010000!st,stm32h7-uartH@ ]0qokaydefaultserial@40011000!st,stm32h7-uartH@ ]0q CABHrxtx disabledi2c@40012000!st,stm32mp15-i2cH@   eventerrorT 0L q disabledi2c@40013000!st,stm32mp15-i2cH@0  eventerrorT!"0L q disabledi2c@40014000!st,stm32mp15-i2cH@@  eventerrorTHI0L q disabledi2c@40015000!st,stm32mp15-i2cH@P  eventerrorTkl0L q disabledcec@40016000 !st,stm32-cecH@` T^0 7cechdmi-cec disableddac@40017000!st,stm32h7-dac-coreH@p07pclk disableddac@1 !st,stm32-dacH disableddac@2 !st,stm32-dacH disabledserial@40018000!st,stm32h7-uartH@ ] 0qokaydefault serial@40019000!st,stm32h7-uartH@ ]!0q CQRHrxtx disabledtimer@44000000!st,stm32-timersHD0T brkuptrg-comcc07intpC   Hch1ch2ch3ch4uptrigcom disabledpwm !st,stm32-pwmR disabledtimer@0!st,stm32h7-timer-triggerH disabledcounter!st,stm32-timer-counter disabledtimer@44001000!st,stm32-timersHD0T+,-. brkuptrg-comcc07intpC/012345Hch1ch2ch3ch4uptrigcom disabledpwm !st,stm32-pwmR disabledtimer@7!st,stm32h7-timer-triggerH disabledcounter!st,stm32-timer-counter disabledserial@44003000!st,stm32h7-uartHD0 ]0q CGHHrxtx disabledspi@44004000!st,stm32h7-spiHD@ T#0LH C%&Hrxtx disabledaudio-controller@44004000!st,stm32h7-i2sHD@ T# C%&Hrxtx disabledspi@44005000!st,stm32h7-spiHDP TT0LI CSTHrxtx disabledtimer@44006000!st,stm32-timersHD` Tt global07int@CijklHch1uptrigcom disabledpwm !st,stm32-pwmR disabledtimer@14!st,stm32h7-timer-triggerH disabledtimer@44007000!st,stm32-timersHDp Tu global07int CmnHch1up disabledpwm !st,stm32-pwmR disabledtimer@15!st,stm32h7-timer-triggerH disabledtimer@44008000!st,stm32-timersHD Tv global07int CopHch1up disabledpwm !st,stm32-pwmR disabledtimer@16!st,stm32h7-timer-triggerH disabledspi@44009000!st,stm32h7-spiHD TU0LJ CUVHrxtx disabledsai@4400a000!st,stm32h7-sai DHDD TWLP disabledaudio-controller@4400a004!st,stm32-sai-sub-aH 07sai_ckCW disabledaudio-controller@4400a024!st,stm32-sai-sub-bH$ 07sai_ckCX disabledsai@4400b000!st,stm32h7-sai DHDD T[LQ disabledaudio-controller@4400b004!st,stm32-sai-sub-aH 07sai_ckCY disabledaudio-controller@4400b024!st,stm32-sai-sub-bH$ 07sai_ckCZ disabledsai@4400c000!st,stm32h7-sai DHDD TrLR disabledaudio-controller@4400c004!st,stm32-sai-sub-aH 07sai_ckCq disabledaudio-controller@4400c024!st,stm32-sai-sub-bH$ 07sai_ckCr disableddfsdm@4400d000!st,stm32mp1-dfsdmHD07dfsdm disabledfilter@0!st,stm32-dfsdm-adcH TnCeHrx disabledfilter@1!st,stm32-dfsdm-adcH ToCfHrx disabledfilter@2!st,stm32-dfsdm-adcH TpCgHrx disabledfilter@3!st,stm32-dfsdm-adcH TqChHrx disabledfilter@4!st,stm32-dfsdm-adcH TsC[Hrx disabledfilter@5!st,stm32-dfsdm-adcH T~C\Hrx disableddma-controller@48000000 !st,stm32-dmaHH`T   /0GLL dma-controller@48001000 !st,stm32-dmaHH`T89:;<DEF0HLL dma-router@48002000!st,stm32h7-dmamuxHH @  0ILLadc@48003000!st,stm32mp1-adc-coreHH0TZ0J7busadcokaydefault - 8DLadc@0!st,stm32mp1-adcHrTC Hrxokaychannel@0HPchannel@1HPchannel@6HPadc@100!st,stm32mp1-adcHrTC Hrxfrvrefintokaychannel@13H vrefintchannel@14Hvddcorechannel@0HPchannel@1HPchannel@2HPmmc@48004000(!st,stm32-sdmmc2arm,pl18xarm,primecell%1HH@ T0x 7apb_pclkL' disabledusb-otg@49000000!st,stm32mp15-hsotgsnps,dwc2HI 0 7otgutmiLdwc2 Tb   otgokaydefault +usb2-phy5:mailbox@4c001000!st,stm32mp1-ipccFHLR]=e rxtx0SqokayLCdcmi@4c006000!st,stm32-dcmiHL` TNM0M7mclkCKHtx disabledrcc@50000000!st,stm32mp1-rccsysconHP]Lpwr@50001000!st,stm32mp1,pwr-regHP- jreg11reg11L3reg18reg18w@w@L4usb33usb332Z2ZLpwr_mcu@50001014!st,stm32mp151-pwr-mcusysconHPL;interrupt-controller@5000d000!st,stm32mp1-extisysconHPLsyscon@50020000!st,stm32mp157-syscfgsysconHP03Ltimer@50021000!st,stm32-lptimerHP ]007muxq disabledpwm!st,stm32-pwm-lpR disabledtrigger@1!st,stm32-lptimer-triggerH disabledcounter!st,stm32-lptimer-counter disabledtimer@50022000!st,stm32-lptimerHP  ]207muxq disabledpwm!st,stm32-pwm-lpR disabledtrigger@2!st,stm32-lptimer-triggerH disabledtimer@50023000!st,stm32-lptimerHP0 ]407muxq disabledpwm!st,stm32-pwm-lpR disabledtimer@50024000!st,stm32-lptimerHP@ ]507muxq disabledpwm!st,stm32-pwm-lpR disabledvrefbuf@50025000!st,stm32-vrefbufHPP`&%04 disabledsai@50027000!st,stm32h7-sai PpHPpPs TL disabledaudio-controller@50027004!st,stm32-sai-sub-aH 07sai_ckCc disabledaudio-controller@50027024!st,stm32-sai-sub-bH$ 07sai_ckCd disabledthermal@50028000!st,stm32-thermalHP T057pclkokayLhash@54002000!st,stm32f756-hashHT  TP0a C Hin disabledrng@54003000 !st,stm32-rngHT00| okaydma-controller@58000000!st,stm32h7-mdmaHX Tz0d  0Lmemory-controller@58002000!st,stm32mp1-fmc2-ebiHX 0y  disabledP`dhlnand-controller@4,0!st,stm32mp1-fmc2-nfcHH   T0HC    Htxrxecc disabledspi@58003000!st,stm32f469-qspiHX0p  qspiqspi_mm T\0CHtxrx0z okaydefaultsleep  flash@0!jedec,spi-norHmmc@58005000(!st,stm32-sdmmc2arm,pl18xarm,primecell%1HXP T10v 7apb_pclk 'okaydefaultopendrainsleep !" "#+6AMY$e%mmc@58007000(!st,stm32-sdmmc2arm,pl18xarm,primecell%1HXp T|0w 7apb_pclk 'okaydefaultopendrainsleep&'(')*rAY+e+crc@58009000!st,stm32f7-crcHX0nokayethernet@5800a000#!st,stm32mp1-dwmacsnps,dwmac-4.20aHX  stmmaceth]= macirq67stmmacethmac-clk-txmac-clk-rxeth-ckptp_refethstp00igh{p,okay-.defaultsleeprgmii/stmmac-axi-config!1L,mdio!snps,dwmac-mdio ;0GVethernet-phy@7HjvL/usb@5800c000 !generic-ohciHX 0o  TJokay51L2usb@5800d000 !generic-ehciHX 0o  TK2okay51display-controller@5a001000!st,stm32-ltdcHZTXY07lcd  disabledwatchdog@5a002000!st,stm32mp1-iwdgHZ 0: 7pclklsiokay usbphyc@5a006000!st,stm32mp1-usbphycHZ`0 3)4okayLusb-phy@08HCL1usb-phy@18HCLserial@5c000000!st,stm32h7-uartH\ ]0q disabledspi@5c001000!st,stm32h7-spiH\ TV0 @0C"#Hrxtx disabledi2c@5c002000!st,stm32mp15-i2cH\   eventerrorT_`0 B qokaydefault5Nestpmic@33 !st,stpmic1H3 ]6okayregulators!st,stpmic1-regulators}++7++88buck1vddcoreOpbuck2vdd_ddrppL7buck3vdd2Z2ZL buck4v3v32Z2ZL+ldo1vdda,@ ,@ TLldo2v2v8**Tldo3vtt_ddr  qldo4vdd_usbTLldo5vdd_sd,@ ,@ T$L$ldo6v1v8w@w@T6vref_ddr vref_ddrboostbst_outTL8pwr_sw1 vbus_otgT RLpwr_sw2vbus_swT Ronkey!st,stpmic1-onkeyT onkey-fallingonkey-risingokaywatchdog!st,stpmic1-wdt disabledeeprom@53 !atmel,24c02HSmrtc@5c004000!st,stm32mp1-rtcH\@0A 7pclkrtc_ck ]okayefuse@5c005000!st,stm32mp15-bsecH\Ppart-number-otp@4Hvrefin-cal@52HRLcalib@5cH\calib@5eH^i2c@5c009000!st,stm32mp15-i2cH\  eventerrorT0 C  q disabledtamp@5c00a000 !st,stm32-tampsysconsimple-mfdH\L<pinctrl@50002000!st,stm32mp157-pinctrl P r `vL9gpio@50002000H0TGPIOAokay9L6gpio@50003000H0UGPIOBokay9gpio@50004000H 0VGPIOCokay9 gpio@50005000H00WGPIODokay90gpio@50006000H@0XGPIOEokay9@gpio@50007000HP0YGPIOFokay9Pgpio@50008000H`0ZGPIOGokay9`gpio@50009000Hp0[GPIOHokay9pgpio@5000a000H0\GPIOIokay 9 L#gpio@5000b000H0]GPIOJ disabledgpio@5000c000H0^GPIOK disabledadc1-ain-0pins[ #adc1-in6-0pins\adc12-ain-0pins#\]^adc12-ain-1L pins\]adc12-usb-cc-pins-0pinscec-0pinscec-sleep-0pinscec-1pinscec-sleep-1pinsdac-ch1-0pinsdac-ch2-0pinsdcmi-0pins<xyz{|~Fwdcmi-sleep-0pins<xyz{|~Fwdcmi-1pins,&z{AK3Mdcmi-sleep-1pins,&z{AK3Mdcmi-2pins4 z@A~Fwdcmi-sleep-2pins4 z@A~Fwrgmii-0pins1 e d m n " B  ! pins2 pins3$ %     rgmii-sleep-0pins1<edmn"B!$%rgmii-1pins1 e d m n " B  ! pins2 pins3$ % v w   rgmii-sleep-1pins1<edmn"B!$%vwrgmii-2L-pins1 e d  n " B k ! pins2 pins3$ % v    rgmii-sleep-2L.pins1<edn"Bk!$%vrgmii-3pins1e m n " B  ! pins2 pins3$ % v    rgmii-sleep-3pins1<edmn"B!$%vrgmii-4pins1d m n " B  pins2$ % v w   rgmii-sleep-4pins10dmn"B$%vwrmii-0pins1m n   ! pins2 $ %  rmii-sleep-0pins1$mn!$%rmii-1pins1! m n pins2 pins3  $ % pins4 rmii-sleep-1pins1$!$%mnrmii-2pins1m n    ! pins2 $ %  rmii-sleep-2pins1$mn!$%fmc-0pins144 5 ; < > ? 0 1 G H I J i pins26 fmc-sleep-0pins845;<>?01GHIJ6ifmc-1pinsT4 5  > ? 0 1 G H I J K L M N O 8 9 : i l fmc-sleep-1pinsT45>?01GHIJKLMNO89:ili2c1-0pins<_i2c1-sleep-0pins<_i2c1-1pins^_i2c1-sleep-1pins^_i2c2-0pinstui2c2-sleep-0pinstui2c2-1pinsui2c2-sleep-1pinsui2c2-2pinsQui2c2-sleep-2pinsQui2c5-0pins  i2c5-sleep-0pins  i2c5-1pins01i2c5-sleep-1pins01i2s2-0pins  i2s2-sleep-0pins  ltdc-0pinspgZrsxyz |OEF}~9lj:8ltdc-sleep-0pinspgZrsxyz |OEF}~9lj:8ltdc-1pinspltdc-sleep-1pinspltdc-2pins1T  36:KLMOt xyz}pins2Nltdc-sleep-2pins1X 36:KLMOtxyz}Nltdc-3pins1gpins2lMmsxy{|OE}Kt h9lj:Lltdc-sleep-3pinspgMmsxy{|OE}Kth9lj:Lmco1-0pins mco1-sleep-0pins mco2-0pinsbmco2-sleep-0pinsbm-can1-0pins1} pins2 m_can1-sleep-0pins}m-can1-1pins1 pins2 m_can1-sleep-1pins  m-can1-2pins1} pins2~ m_can1-sleep-2pins}~m-can2-0pins1 pins2 m_can2-sleep-0pinspwm1-0pins IKN pwm1-sleep-0pins IKNpwm1-1pinsI pwm1-sleep-1pinsIpwm1-2pinsKpwm1-sleep-2pinsKpwm2-0pins pwm2-sleep-0pinspwm3-0pins' pwm3-sleep-0pins'pwm3-1pinspwm3-sleep-1pinspwm4-0pins>? pwm4-sleep-0pins>?pwm4-1pins= pwm4-sleep-1pins=pwm5-0pins{ pwm5-sleep-0pins{pwm5-1pins {|pwm5-sleep-1pins {|pwm8-0pins pwm8-sleep-0pinspwm8-1pins)pwm8-sleep-1pins)pwm12-0pinsv pwm12-sleep-0pinsvqspi-clk-0LpinsZ qspi-clk-sleep-0LpinsZqspi-bk1-0LpinsX Y W V qspi-bk1-sleep-0LpinsXYWVqspi-bk2-0pinsr s j g qspi-bk2-sleep-0pinsrsjgqspi-cs1-0Lpins qspi-cs1-sleep-0Lpinsqspi-cs2-0pins qspi-cs2-sleep-0pins sai2a-0pins @ sai2a-sleep-0pins@sai2a-1pins1  = sai2a-sleep-1pins =sai2a-2pins = ; < sai2a-sleep-2pins =;<sai2b-0pins1 L M N pins2[ sai2b-sleep-0pins[LMNsai2b-1pins[ sai2b-sleep-1pins[sai2b-2pins1[ sai2b-sleep-2pins[sai2b-3pins1 r s pins2[ sai2b-sleep-3pins1r s[sai4a-0pins sai4a-sleep-0pinssdmmc1-b4-0Lpins1( ) * + 2 pins2, sdmmc1-b4-od-0L pins1( ) * + pins2, pins32 sdmmc1-b4-init-0pins1( ) * + sdmmc1-b4-sleep-0L!pins()*+,2sdmmc1-b4-1pins1( ) F + 2 pins2, sdmmc1-b4-od-1pins1( ) F + pins2, pins32 sdmmc1-b4-sleep-1pins()F+,2sdmmc1-dir-0pins1 R '  pins2D sdmmc1-dir-init-0pins1 R '  sdmmc1-dir-sleep-0pinsR'Dsdmmc1-dir-1Lpins1 R N  pins2D sdmmc1-dir-sleep-1L"pinsRNDsdmmc2-b4-0L&pins1    f pins2C sdmmc2-b4-od-0L(pins1    pins2C pins3f sdmmc2-b4-sleep-0L)pinsCfsdmmc2-b4-1pins1    f pins2C sdmmc2-b4-od-1pins1    pins2C pins3f sdmmc2-d47-0pins E 3 sdmmc2-d47-sleep-0pins E3sdmmc2-d47-1pins & ' sdmmc2-d47-sleep-1pins &'sdmmc2-d47-2L'pins  & ' sdmmc2-d47-sleep-2L*pins&'sdmmc2-d47-3pins E ' sdmmc2-d47-sleep-3pins E'sdmmc2-d47-4pins & 3 sdmmc2-d47-sleep-4pins &3sdmmc3-b4-0pins1P T U 7 Q pins2o sdmmc3-b4-od-0pins1P T U 7 pins2o pins3Q sdmmc3-b4-sleep-0pinsPTU7oQsdmmc3-b4-1pins1P T 5 7 0 pins2o sdmmc3-b4-od-1pins1P T 5 7 pins2o pins30 sdmmc3-b4-sleep-1pinsPT57o0spdifrx-0pinsl spdifrx-sleep-0pinslspi1-1pins1pins2spi2-0pins1pins2spi2-1pins1pins2spi2-2pins1pins2 spi4-0pinsLFpins2Mspi5-0pins1WYpins2Xstusb1600-0pinsuart4-0pins1kpins2 uart4-idle-0pins1kpins2 uart4-sleep-0pinskuart4-1Lpins11 pins2 uart4-2pins1kpins2 uart4-3pins1 pins2 uart4-idle-3pins1 pins2 uart4-sleep-3pins uart5-0pins1pins2 uart7-0L pins1Hpins2 GJIuart7-1pins1Wpins2Vuart7-2pins1Hpins2Guart7-idle-2pins1Hpins2Guart7-sleep-2pinsHGuart8-0pins1A pins2@ uart8rtscts-0pinsg j usart1-0pins1 pins2 usart1-idle-0pins1  usart1-sleep-0pins  usart2-0pins1U4pins263usart2-sleep-0pinsU463usart2-1pins1Upins2TOusart2-sleep-1pinsUTOusart2-2pins154pins263usart2-idle-2pins153pins24pins36usart2-sleep-2pins5463usart3-0pins1pins2 usart3-idle-0pins1pins2 usart3-sleep-0pinsusart3-1pins1h pins2 usart3-idle-1pins1pins2h pins3 usart3-sleep-1pinshusart3-2pins1h pins2 usart3-idle-2pins1pins2h pins3 usart3-sleep-2pinshusart3-3pins1h pins29;usart3-idle-3pins1 h;pins29usart3-sleep-3pinsh;9usart3-4pins1h pins2;usart3-idle-4pins1;pins2h pins3usart3-sleep-4pinsh;usart3-5pins1<pins2 ;usbotg-hs-0Lpins usbotg-fs-dp-dm-0pins  pinctrl@54004000!st,stm32mp157-z-pinctrl T@r `vL:gpio@54004000H0_GPIOZ okay:L0i2c2-0pinsi2c2-sleep-0pinsi2c4-0L5pinsi2c4-sleep-0pinsi2c6-0pinsi2c6-sleep-0pinsspi1-0pins1pins2spi1-sleep-0pins usart1-1pins1pins2usart1-idle-1pins1pins2usart1-sleep-1pinsahb!st,mlahbsimple-bus$'800m4@10000000!st,stm32mp1-m4H08 !mcu_rst 2  E; T<D f<Hokayy=>?@AB CCCCvq0vq1shutdowndetachrTDaliases/soc/spi@58003000/soc/ethernet@5800a000/soc/mmc@58005000/soc/mmc@58007000/soc/serial@40010000/soc/serial@40018000memory@c0000000retram@38000000!shared-dma-poolH8L=chosenserial0:115200n8regulator-sd_switch!regulator-gpio sd_switchw@,@ voltage %#w@,@ L% #address-cells#size-cellsmodelcompatibleclock-frequencydevice_typeregphandleinterruptsinterrupt-affinityinterrupt-parentmethod#interrupt-cellsinterrupt-controller#clock-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisst,syscfgstatusrangesinterrupt-namesclocksclock-namesdmasdma-names#pwm-cellsinterrupts-extendedwakeup-sourceresets#sound-dai-cellspinctrl-namespinctrl-0st,syscfg-fmpi2c-analog-filter#io-channel-cellsuart-has-rtscts#dma-cellsst,mem2memdma-requestsdma-mastersdma-channelsvdd-supplyvdda-supplyvref-supplyst,min-sample-time-nsnvmem-cellsnvmem-cell-nameslabelarm,primecell-periphidcap-sd-highspeedcap-mmc-highspeedmax-frequencyreset-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeotg-revusb33d-supplyphy-namesphysvbus-supply#mbox-cellsst,proc-id#reset-cellsvdd_3v3_usbfs-supplyregulator-nameregulator-min-microvoltregulator-max-microvolt#thermal-sensor-cellsdma-maxburstreg-namespinctrl-1spi-rx-bus-widthspi-max-frequencypinctrl-2cd-gpiosdisable-wpst,sig-dirst,neg-edgest,use-ckinvmmc-supplyvqmmc-supplymmc-ddr-1_8vno-sdno-sdionon-removablest,sysconsnps,mixed-burstsnps,pblsnps,en-tx-lpi-clockgatingsnps,axi-configsnps,tsophy-modemax-speedphy-handlesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenreset-gpiosreset-delay-usreset-post-delay-usrxc-skew-psrxdv-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxc-skew-pstxen-skew-pstxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-pscompaniontimeout-secvdda1v1-supplyvdda1v8-supply#phy-cellsphy-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsldo1-supplyldo2-supplyldo3-supplyldo5-supplyldo6-supplypwr_sw1-supplypwr_sw2-supplyregulator-always-onregulator-initial-moderegulator-over-current-protectionregulator-boot-onregulator-enable-ramp-delayregulator-active-dischargepagesizest,packagegpio-controller#gpio-cellsst,bank-namengpiosgpio-rangespinmuxbias-disabledrive-open-drainslew-ratebias-pull-updrive-push-pullbias-pull-downst,bank-ioportdma-rangesst,syscfg-holdbootst,syscfg-pddsst,syscfg-rsc-tblst,syscfg-m4-statememory-regionmboxesmbox-namesspi0ethernet0mmc0mmc1serial0serial1no-mapstdout-pathregulator-typegpios-states