8( ?`google,veyron-speedy-rev9google,veyron-speedy-rev8google,veyron-speedy-rev7google,veyron-speedy-rev6google,veyron-speedy-rev5google,veyron-speedy-rev4google,veyron-speedy-rev3google,veyron-speedy-rev2google,veyron-speedygoogle,veyronrockchip,rk3288&7Google Speedyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000/mmc@ff0c0000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12  (7@ELrf rcpu@501cpuarm,cortex-a12  (7@ELrrcpu@502cpuarm,cortex-a12  (7@ELrrcpu@503cpuarm,cortex-a12  (7@ELrropp-table-0operating-points-v2zropp-126000000 opp-216000000  opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJopp-1608000000_" opp-1704000000epopp-1800000000kI\reserved-memorydma-unusable@fe000000 oscillator fixed-clockn6xin24mr timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea   pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр EDrv biuciuciu-driveciu-sample,  @ 7resetCokayJTfw  Z defaultmmc@ff0d0000rockchip,rk3288-dw-mshcр EEsw biuciuciu-driveciu-sample, ! @ 7resetCokayJf!.DO default mmc@ff0e0000rockchip,rk3288-dw-mshcр EFtx biuciuciu-driveciu-sample, " @ 7reset Cdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcр EGuy biuciuciu-driveciu-sample, # @ 7resetCokayJT]DO default saradc@ff100000rockchip,saradc  $lEI[ saradcapb_pclk W 7saradc-apb Cdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEAR spiclkapb_pclk~  txrx , default !"# Cokayec@0google,cros-ec-spi &  default$-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb D4;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBS spiclkapb_pclk~ txrx - default%&'(  Cdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECT spiclkapb_pclk~txrx . default)*+, CokayA flash@0jedec,spi-nor i2c@ff140000rockchip,rk3288-i2c  > i2cEM default-CokayT2ldtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c  ? i2cEO default. Cdisabledi2c@ff160000rockchip,rk3288-i2c  @ i2cEP default/CokayT2l,ts3a227e@3b ti,ts3a227e ;&0 default1rtrackpad@15elan,ekth3000 &  default23i2c@ff170000rockchip,rk3288-i2c  A i2cEQ default4 Cdisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart  7EMU baudclkapb_pclk~txrx default 567Cokaybluetooth default 89:brcm,bcm43540-bt ; ; ; -serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart  8ENV baudclkapb_pclk~txrx default<Cokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart i 9EOW baudclkapb_pclk default=Cokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart  :EPX baudclkapb_pclk~txrx default> Cdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart  ;EQY baudclkapb_pclk~  txrx default? Cdisableddma-controller@ff250000arm,pl330arm,primecell %@,7RE  apb_pclkrthermal-zonesreserve-thermali@cpu-thermalid@tripscpu_alert0passiverAcpu_alert1ppassiverBcpu_crit_ criticalcooling-mapsmap0A0map1B0gpu-thermalid@tripsgpu_alert08passiverCgpu_crit_ criticalcooling-mapsmap0C Dtsadc@ff280000rockchip,rk3288-tsadc ( %EHZ tsadcapb_pclk  7tsadc-apb initdefaultsleepEFEGHCokay-r@ethernet@ff290000rockchip,rk3288-gmac )Hmacirqeth_wake_irqG8Efgc]M stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B 7stmmaceth Cdisabledusb@ff500000 generic-ehci P EXH]usbCokaygusb@ff520000 generic-ohci R )EXH]usb Cdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 T E otg}hostXI ]usb2-phyCokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 X E otg}host@@ XJ ]usb2-phyCokayzJusb@ff5c0000 generic-ehci \ E Cdisableddma-controller@ff600000arm,pl330arm,primecell `@,7RE  apb_pclk Cdisabledi2c@ff650000rockchip,rk3288-i2c e < i2cEL defaultKCokayT2ldpmic@1brockchip,rk808 xin32kwifibt_32kin&0 defaultL +7CO[Mgs3MMrregulatorsDCDC_REG1vdd_arm q  $qr regulator-state-mem9DCDC_REG2vdd_gpu 5 $qrregulator-state-mem9DCDC_REG3 vcc135_ddrregulator-state-memRDCDC_REG4vcc_18w@ w@rregulator-state-memRjw@LDO_REG1 vcc33_io2Z 2Zr3regulator-state-memRj2ZLDO_REG3vdd_10B@ B@regulator-state-memRjB@LDO_REG7vdd10_lcd_pwren_h&% &%regulator-state-mem9SWITCH_REG1 vcc33_lcdrcregulator-state-mem9LDO_REG6 vcc18_codecw@ w@rdregulator-state-mem9LDO_REG4 vccio_sdw@ 2Zrregulator-state-mem9LDO_REG5 vcc33_sd2Z 2Zrregulator-state-mem9LDO_REG8 vcc33_ccd2Z 2Zregulator-state-mem9i2c@ff660000rockchip,rk3288-i2c f = i2cEN defaultNCokayT2l max98090@10maxim,max98090 &O mclkEq defaultPrpwm@ff680000rockchip,rk3288-pwm h defaultQE_Cokayrpwm@ff680010rockchip,rk3288-pwm h defaultRE_Cokayrpwm@ff680020rockchip,rk3288-pwm h  defaultSE_ Cdisabledpwm@ff680030rockchip,rk3288-pwm h0 defaultTE_ Cdisabledsram@ff700000 mmio-sram ppsmp-sram@0rockchip,rk3066-smp-sram sram@ff720000#rockchip,rk3288-pmu-srammmio-sram rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd srpower-controller!rockchip,rk3288-power-controllerh rhpower-domain@9 Echgfdehilkj$UVWXYZ[\]power-domain@11 Eop^_power-domain@12 E`power-domain@13 Eabreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon tclock-controller@ff760000rockchip,rk3288-cru vE  xin24mGHjk$#gׄeрxhрxhrsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd wrGedp-phyrockchip,rk3288-dp-phyEh 24m Cokayrxio-domains"rockchip,rk3288-io-voltage-domainCokay 3  + 93 I3 Wc c od |usbphyrockchip,rk3288-usb-phyCokayusb-phy@320   E] phyclk  7phy-resetrJusb-phy@334  4E^ phyclk  7phy-resetrHusb-phy@348  HE_ phyclk  7phy-resetrIwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt Ep OCokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  ET  mclkhclk~etx 6 defaultfG Cdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s   5ER i2s_clki2s_hclk~eetxrx defaultg  Cokayrcrypto@ff8a0000rockchip,rk3288-crypto @ 0 E} aclkhclksclkapb_pclk  7crypto-rstiommu@ff900800rockchip,iommu @ E  aclkiface  Cdisablediommu@ff914000rockchip,iommu  @P E  aclkiface   Cdisabledrga@ff920000rockchip,rk3288-rga  Ej aclkhclksclk h  ilm 7coreaxiahbvop@ff930000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop h  def 7axiahbdclk iCokayportr endpoint@0  jr~endpoint@1  kryendpoint@2  lrsendpoint@3  mrviommu@ff930300rockchip,iommu  E  aclkiface h  Cokayrivop@ff940000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop h   7axiahbdclk nCokayportr endpoint@0  orendpoint@1  przendpoint@2  qrtendpoint@3  rrwiommu@ff940300rockchip,iommu  E  aclkiface h  Cokayrndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi @ E~d  refpclk h G Cdisabledportsport@0 endpoint@0  srlendpoint@1  trqport@1 lvds@ff96c000rockchip,rk3288-lvds @Eg  pclk_lvds lcdcu h G Cdisabledportsport@0 endpoint@0  vrmendpoint@1  wrrport@1 dp@ff970000rockchip,rk3288-dp @ bEic dppclkXx]dp h  o7dpGCokay portsport@0 endpoint@0  yrkendpoint@1  zrpport@1 endpoint@0  {rhdmi@ff980000rockchip,rk3288-dw-hdmi  G gEhmn iahbisfrcec h Cokay defaultunwedge|}rportsportendpoint@0  ~rjendpoint@1  rovideo-codec@ff9a0000rockchip,rk3288-vpu    HvepuvdpuE  aclkhclk  h iommu@ff9a0800rockchip,iommu  E  aclkiface  h riommu@ff9c0440rockchip,iommu  @@@ oE  aclkiface  Cdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760 $ HjobmmugpuE( h Cokay 'rDopp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon raqos@ffaa0080rockchip,rk3288-qossyscon rbqos@ffad0000rockchip,rk3288-qossyscon rVqos@ffad0100rockchip,rk3288-qossyscon  rWqos@ffad0180rockchip,rk3288-qossyscon  rXqos@ffad0400rockchip,rk3288-qossyscon  rYqos@ffad0480rockchip,rk3288-qossyscon  rZqos@ffad0500rockchip,rk3288-qossyscon  rUqos@ffad0800rockchip,rk3288-qossyscon  r[qos@ffad0880rockchip,rk3288-qossyscon  r\qos@ffad0900rockchip,rk3288-qossyscon r]qos@ffae0000rockchip,rk3288-qossyscon r`qos@ffaf0000rockchip,rk3288-qossyscon r^qos@ffaf0080rockchip,rk3288-qossyscon r_dma-controller@ffb20000arm,pl330arm,primecell @,7RE  apb_pclkreefuse@ffb40000rockchip,rk3288-efuse Eq  pclk_efusecpu-id@7 cpu_leakage@17 interrupt-controller@ffc01000 arm,gic-400 3 H@  @ `   rpinctrlrockchip,rk3288-pinctrlG defaultsleepgpio@ff750000rockchip,gpio-bank u QE@ Y i 3 H uPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTr0gpio@ff780000rockchip,gpio-bank x REA Y i 3 Hgpio@ff790000rockchip,gpio-bank y SEB Y i 3 HZ uCONFIG0CONFIG1CONFIG2CONFIG3PWRLIMIT#_CPUEMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENrgpio@ff7a0000rockchip,gpio-bank z TEC Y i 3 H uFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank { UED Y i 3 H uUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEr;gpio@ff7c0000rockchip,gpio-bank | VEE Y i 3 HA uSPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENrgpio@ff7d0000rockchip,gpio-bank } WEF Y i 3 H uI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDrOgpio@ff7e0000rockchip,gpio-bank ~ XEG Y i 3 H uLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKEDP_HOTPLUGDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDr gpio@ff7f0000rockchip,gpio-bank  YEH Y i 3 H^ uRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc r|hdmi-ddc-unwedge r}vcc50-hdmi-en rpcfg-output-low rpcfg-pull-up rpcfg-pull-down rpcfg-pull-none rpcfg-pull-none-12ma  rsuspendglobal-pwroff rddrio-pwroff rddr0-retention rddr1-retention suspend-l-wake rsuspend-l-sleep redpedp-hpd  i2c0i2c0-xfer rKi2c1i2c1-xfer r-i2c2i2c2-xfer   rNi2c3i2c3-xfer r.i2c4i2c4-xfer r/i2c5i2c5-xfer r4i2s0i2s0-bus` rglcdclcdc-ctl@ rusdmmcsdmmc-clk rsdmmc-cmd rsdmmc-cd sdmmc-bus1 sdmmc-bus4@ rsdmmc-cd-disabled rsdmmc-cd-pin rsdio0sdio0-bus1 sdio0-bus4@ rsdio0-cmd rsdio0-clk rsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h rbt-enable-l r9bt-host-wake bt-host-wake-l r8bt-dev-wake-sleep bt-dev-wake-awake bt-dev-wake r:sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk remmc-cmd remmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 remmc-reset  rspi0spi0-clk  r spi0-cs0  r#spi0-tx r!spi0-rx r"spi0-cs1 spi1spi1-clk  r%spi1-cs0  r(spi1-rx r'spi1-tx r&spi2spi2-cs1 spi2-clk r)spi2-cs0 r,spi2-rx r+spi2-tx  r*uart0uart0-xfer r5uart0-cts r6uart0-rts r7uart1uart1-xfer  r<uart1-cts  uart1-rts  uart2uart2-xfer r=uart3uart3-xfer r>uart3-cts  uart3-rts  uart4uart4-xfer r?uart4-cts  uart4-rts  tsadcotp-pin rEotp-out rFpwm0pwm0-pin rQpwm1pwm1-pin rRpwm2pwm2-pin rSpwm3pwm3-pin rTgmacrgmii-pins  rmii-pins spdifspdif-tx  rfpcfg-pull-none-drv-8ma  rpcfg-pull-up-drv-8ma  pcfg-output-high rbuttonspwr-key-l rap-lid-int-l rpmicpmic-int-l rLdvs-1  dvs-2 rebootap-warm-reset-h rrecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det rint-codec rPmic-det  rheadsetts3a227e-int-l r1backlightbl_pwr_en  rbl-en rlcdlcd-en ravdd-1v8-disp-en  rchargerac-present-ap rcros-ecec-int r$trackpadtrackpad-int r2usb-hosthost1-pwr-en rusbotg-pwren-h rbuck-5vdrv-5v rchosen serial2:115200n8memorymemory power-button gpio-keys defaultkey-power Power 0 t dgpio-restart gpio-restart 0  default emmc-pwrseqmmc-pwrseq-emmc default  rsdio-pwrseqmmc-pwrseq-simpleE  ext_clock default ;rvcc-5vregulator-fixedvcc_5vLK@ LK@ & 1 D  defaultrMvcc33-sysregulator-fixed vcc33_sys2Z 2Z &rvcc50-hdmiregulator-fixed vcc50_hdmi &M 1 D defaultvdd-logicpwm-regulator vdd_logic I N Y{ m~ p$sound!rockchip,rockchip-audio-max98090 default VEYRON-I2S   O O   backlight-regulatorregulator-fixed 1 D  defaultbacklight_regulator & :rpanel-regulatorregulator-fixed 1 D  defaultpanel_regulator &rvcc18-lcdregulator-fixed 1 D  default vcc18_lcd &backlightpwm-backlight % 7 N g  default IB@ t   rpanelinnolux,n116bgeCokay  panel-timingl V  <       portsportendpoint r{gpio-charger gpio-charger !mains 0 defaultlid-switch gpio-keys defaultswitch-lid Lid 0  . vccsysregulator-fixedvccsysrvcc5-host1-regulatorregulator-fixed 1 D0  default vcc5_host1vcc5v-otg-regulatorregulator-fixed 1 D0  default vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type