8( google,veyron-minnie-rev4google,veyron-minnie-rev3google,veyron-minnie-rev2google,veyron-minnie-rev1google,veyron-minnie-rev0google,veyron-minniegoogle,veyronrockchip,rk3288&7Google Minniealiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000/mmc@ff0c0000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12  (7@ELrf rcpu@501cpuarm,cortex-a12  (7@ELrrcpu@502cpuarm,cortex-a12  (7@ELrrcpu@503cpuarm,cortex-a12  (7@ELrropp-table-0operating-points-v2zropp-126000000 opp-216000000  opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJopp-1608000000_" opp-1704000000epopp-1800000000kI\reserved-memorydma-unusable@fe000000 oscillator fixed-clockn6xin24mr timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea   pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр EDrv biuciuciu-driveciu-sample,  @ 7resetCokayJTfw  Z defaultmmc@ff0d0000rockchip,rk3288-dw-mshcр EEsw biuciuciu-driveciu-sample, ! @ 7resetCokayJf!.DO default mmc@ff0e0000rockchip,rk3288-dw-mshcр EFtx biuciuciu-driveciu-sample, " @ 7reset Cdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcр EGuy biuciuciu-driveciu-sample, # @ 7resetCokayJT]DO default saradc@ff100000rockchip,saradc  $lEI[ saradcapb_pclk W 7saradc-apb Cdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEAR spiclkapb_pclk~  txrx , default !"# Cokayec@0google,cros-ec-spi &  default$-i2c-tunnelgoogle,cros-ec-i2c-tunnelbq27500@55 ti,bq27500 Ukeyboard-controllergoogle,cros-ec-keyb D ;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBS spiclkapb_pclk~ txrx - default%&'(  Cdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECT spiclkapb_pclk~txrx . default)*+, Cokay flash@0jedec,spi-nor i2c@ff140000rockchip,rk3288-i2c  > i2cEM default-Cokay+2Cdtpm@20infineon,slb9645tt Zi2c@ff150000rockchip,rk3288-i2c  ? i2cEO default.Cokay+2C,touchscreen@10elan,ekth3500 &/ default01 r/~22i2c@ff160000rockchip,rk3288-i2c  @ i2cEP default3Cokay+2C,ts3a227e@3b ti,ts3a227e ;&4 default5rtrackpad@15elan,ekth3000 &  default67i2c@ff170000rockchip,rk3288-i2c  A i2cEQ default8 Cdisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart  7EMU baudclkapb_pclk~txrx default 9:;Cokaybluetooth default <=>brcm,bcm43540-bt ? ? ?-serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart  8ENV baudclkapb_pclk~txrx default@Cokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart i 9EOW baudclkapb_pclk defaultACokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart  :EPX baudclkapb_pclk~txrx defaultB Cdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart  ;EQY baudclkapb_pclk~  txrx defaultC Cdisableddma-controller@ff250000arm,pl330arm,primecell %@)4OE  apb_pclkrthermal-zonesreserve-thermalf|Dcpu-thermalfd|Dtripscpu_alert0ppassiverEcpu_alert1$passiverFcpu_crit criticalcooling-mapsmap0E0map1F0gpu-thermalfd|Dtripsgpu_alert04passiverGgpu_crit criticalcooling-mapsmap0G Htsadc@ff280000rockchip,rk3288-tsadc ( %EHZ tsadcapb_pclk  7tsadc-apb initdefaultsleepIJIKHCokay*rDethernet@ff290000rockchip,rk3288-gmac )Emacirqeth_wake_irqK8Efgc]M stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B 7stmmaceth Cdisabledusb@ff500000 generic-ehci P EULZusbCokaydusb@ff520000 generic-ohci R )EULZusb Cdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 T E otgzhostUM Zusb2-phyCokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 X E otgzhost@@ UN Zusb2-phyCokayzNusb@ff5c0000 generic-ehci \ E Cdisableddma-controller@ff600000arm,pl330arm,primecell `@)4OE  apb_pclk Cdisabledi2c@ff650000rockchip,rk3288-i2c e < i2cEL defaultOCokay+2Cdpmic@1brockchip,rk808 xin32kwifibt_32kin&4 default PQR(4@LXSdp|7SSrregulatorsDCDC_REG1vdd_arm q  !qr regulator-state-mem6DCDC_REG2vdd_gpu 5 !qrregulator-state-mem6DCDC_REG3 vcc135_ddrregulator-state-memODCDC_REG4vcc_18w@ w@rregulator-state-memOgw@LDO_REG1 vcc33_io2Z 2Zr7regulator-state-memOg2ZLDO_REG3vdd_10B@ B@regulator-state-memOgB@LDO_REG7vdd10_lcd_pwren_h&% &%regulator-state-mem6SWITCH_REG1 vcc33_lcdriregulator-state-mem6LDO_REG6 vcc18_codecw@ w@rjregulator-state-mem6LDO_REG4 vccio_sdw@ 2Zrregulator-state-mem6LDO_REG5 vcc33_sd2Z 2Zrregulator-state-mem6LDO_REG8 vcc33_ccd2Z 2Zregulator-state-mem6LDO_REG22Z 2Z vcc33_touchr2regulator-state-mem6SWITCH_REG2 vcc5v_touchregulator-state-mem6i2c@ff660000rockchip,rk3288-i2c f = i2cEN defaultTCokay+2C max98090@10maxim,max98090 &U mclkEq defaultVrpwm@ff680000rockchip,rk3288-pwm h defaultWE_Cokayrpwm@ff680010rockchip,rk3288-pwm h defaultXE_Cokayrpwm@ff680020rockchip,rk3288-pwm h  defaultYE_ Cdisabledpwm@ff680030rockchip,rk3288-pwm h0 defaultZE_ Cdisabledsram@ff700000 mmio-sram ppsmp-sram@0rockchip,rk3066-smp-sram sram@ff720000#rockchip,rk3288-pmu-srammmio-sram rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd srpower-controller!rockchip,rk3288-power-controllerh rnpower-domain@9 Echgfdehilkj$[\]^_`abcpower-domain@11 Eopdepower-domain@12 Efpower-domain@13 Eghreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon tclock-controller@ff760000rockchip,rk3288-cru vE  xin24mKHjk$#gׄeрxhрxhrsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd wrKedp-phyrockchip,rk3288-dp-phyEh 24m Cokayr~io-domains"rockchip,rk3288-io-voltage-domainCokay 7  ( 67 F7 Ti ` lj yusbphyrockchip,rk3288-usb-phyCokayusb-phy@320   E] phyclk  7phy-resetrNusb-phy@334  4E^ phyclk  7phy-resetrLusb-phy@348  HE_ phyclk  7phy-resetrMwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt Ep OCokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  ET  mclkhclk~ktx 6 defaultlK Cdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s   5ER i2s_clki2s_hclk~kktxrx defaultm  Cokayrcrypto@ff8a0000rockchip,rk3288-crypto @ 0 E} aclkhclksclkapb_pclk  7crypto-rstiommu@ff900800rockchip,iommu @ E  aclkiface  Cdisablediommu@ff914000rockchip,iommu  @P E  aclkiface   Cdisabledrga@ff920000rockchip,rk3288-rga  Ej aclkhclksclk n  ilm 7coreaxiahbvop@ff930000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop n  def 7axiahbdclk oCokayportr endpoint@0  prendpoint@1  qrendpoint@2  rryendpoint@3  sr|iommu@ff930300rockchip,iommu  E  aclkiface n  Cokayrovop@ff940000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop n   7axiahbdclk tCokayportr endpoint@0  urendpoint@1  vrendpoint@2  wrzendpoint@3  xr}iommu@ff940300rockchip,iommu  E  aclkiface n  Cokayrtdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi @ E~d  refpclk n K Cdisabledportsport@0 endpoint@0  yrrendpoint@1  zrwport@1 lvds@ff96c000rockchip,rk3288-lvds @Eg  pclk_lvds lcdc{ n K Cdisabledportsport@0 endpoint@0  |rsendpoint@1  }rxport@1 dp@ff970000rockchip,rk3288-dp @ bEic dppclkU~Zdp n  o7dpKCokay defaultportsport@0 endpoint@0  rqendpoint@1  rvport@1 endpoint@0  rhdmi@ff980000rockchip,rk3288-dw-hdmi  K gEhmn iahbisfrcec n Cokay defaultunwedgerportsportendpoint@0  rpendpoint@1  ruvideo-codec@ff9a0000rockchip,rk3288-vpu    EvepuvdpuE  aclkhclk  n iommu@ff9a0800rockchip,iommu  E  aclkiface  n riommu@ff9c0440rockchip,iommu  @@@ oE  aclkiface  Cdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760 $ EjobmmugpuE( n Cokay rHopp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon rgqos@ffaa0080rockchip,rk3288-qossyscon rhqos@ffad0000rockchip,rk3288-qossyscon r\qos@ffad0100rockchip,rk3288-qossyscon  r]qos@ffad0180rockchip,rk3288-qossyscon  r^qos@ffad0400rockchip,rk3288-qossyscon  r_qos@ffad0480rockchip,rk3288-qossyscon  r`qos@ffad0500rockchip,rk3288-qossyscon  r[qos@ffad0800rockchip,rk3288-qossyscon  raqos@ffad0880rockchip,rk3288-qossyscon  rbqos@ffad0900rockchip,rk3288-qossyscon rcqos@ffae0000rockchip,rk3288-qossyscon rfqos@ffaf0000rockchip,rk3288-qossyscon rdqos@ffaf0080rockchip,rk3288-qossyscon redma-controller@ffb20000arm,pl330arm,primecell @)4OE  apb_pclkrkefuse@ffb40000rockchip,rk3288-efuse Eq  pclk_efusecpu-id@7 cpu_leakage@17 interrupt-controller@ffc01000 arm,gic-400 & ;@  @ `   rpinctrlrockchip,rk3288-pinctrlK defaultsleepgpio@ff750000rockchip,gpio-bank u QE@ L \ & ; hPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTr4gpio@ff780000rockchip,gpio-bank x REA L \ & ;gpio@ff790000rockchip,gpio-bank y SEB L \ & ; hCONFIG0CONFIG1CONFIG2CONFIG3PROCHOT#EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPr/gpio@ff7a0000rockchip,gpio-bank z TEC L \ & ; hFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank { UED L \ & ; hUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKdev_wakeWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEr?gpio@ff7c0000rockchip,gpio-bank | VEE L \ & ;U hVolum_Up#Volum_Down#SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENrgpio@ff7d0000rockchip,gpio-bank } WEF L \ & ; hI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDrUgpio@ff7e0000rockchip,gpio-bank ~ XEG L \ & ; hLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDr gpio@ff7f0000rockchip,gpio-bank  YEH L \ & ;^ hRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 xhdmi-cec-c7 xhdmi-ddc xrhdmi-ddc-unwedge xrvcc50-hdmi-en xrpcfg-output-low rpcfg-pull-up rpcfg-pull-down rpcfg-pull-none rpcfg-pull-none-12ma  rsuspendglobal-pwroff xrddrio-pwroff xrddr0-retention xrddr1-retention xsuspend-l-wake xrsuspend-l-sleep xredpedp-hpd x ri2c0i2c0-xfer xrOi2c1i2c1-xfer xr-i2c2i2c2-xfer x  rTi2c3i2c3-xfer xr.i2c4i2c4-xfer xr3i2c5i2c5-xfer xr8i2s0i2s0-bus` xrmlcdclcdc-ctl@ xr{sdmmcsdmmc-clk xrsdmmc-cmd xrsdmmc-cd xsdmmc-bus1 xsdmmc-bus4@ xrsdmmc-cd-disabled xrsdmmc-cd-pin xrsdio0sdio0-bus1 xsdio0-bus4@ xrsdio0-cmd xrsdio0-clk xrsdio0-cd xsdio0-wp xsdio0-pwr xsdio0-bkpwr xsdio0-int xwifienable-h xrbt-enable-l xr=bt-host-wake xbt-host-wake-l xr<bt-dev-wake-sleep xbt-dev-wake-awake xbt-dev-wake xr>sdio1sdio1-bus1 xsdio1-bus4@ xsdio1-cd xsdio1-wp xsdio1-bkpwr xsdio1-int xsdio1-cmd xsdio1-clk xsdio1-pwr x emmcemmc-clk xremmc-cmd xremmc-pwr x emmc-bus1 xemmc-bus4@ xemmc-bus8 xremmc-reset x rspi0spi0-clk x r spi0-cs0 x r#spi0-tx xr!spi0-rx xr"spi0-cs1 xspi1spi1-clk x r%spi1-cs0 x r(spi1-rx xr'spi1-tx xr&spi2spi2-cs1 xspi2-clk xr)spi2-cs0 xr,spi2-rx xr+spi2-tx x r*uart0uart0-xfer xr9uart0-cts xr:uart0-rts xr;uart1uart1-xfer x r@uart1-cts x uart1-rts x uart2uart2-xfer xrAuart3uart3-xfer xrBuart3-cts x uart3-rts x uart4uart4-xfer xrCuart4-cts x uart4-rts x tsadcotp-pin x rIotp-out x rJpwm0pwm0-pin xrWpwm1pwm1-pin xrXpwm2pwm2-pin xrYpwm3pwm3-pin xrZgmacrgmii-pins x rmii-pins xspdifspdif-tx x rlpcfg-pull-none-drv-8ma  rpcfg-pull-up-drv-8ma  pcfg-output-high rbuttonspwr-key-l xrap-lid-int-l xrvolum-down-l x rvolum-up-l x rpmicpmic-int-l xrPdvs-1 x rQdvs-2 xrRrebootap-warm-reset-h x rrecovery-switchrec-mode-l x tpmtpm-int-h xwrite-protectfw-wp-ap xcodechp-det xrint-codec xrVmic-det x rheadsetts3a227e-int-l xr5backlightbl_pwr_en x rbl-en xrlcdlcd-en xravdd-1v8-disp-en x rchargerac-present-ap xrcros-ecec-int xr$trackpadtrackpad-int xr6usb-hosthost1-pwr-en x rusbotg-pwren-h x rbuck-5vdrv-5v xrprochotgpio-prochot xtouchscreentouch-int xr0touch-rst xr1chosen serial2:115200n8memorymemory power-button gpio-keys defaultkey-power Power 4 t dgpio-restart gpio-restart 4  default emmc-pwrseqmmc-pwrseq-emmc default r/ rsdio-pwrseqmmc-pwrseq-simpleE  ext_clock default r?rvcc-5vregulator-fixedvcc_5vLK@ LK@   +  defaultrSvcc33-sysregulator-fixed vcc33_sys2Z 2Z rvcc50-hdmiregulator-fixed vcc50_hdmi S  + defaultvdd-logicpwm-regulator vdd_logic 0 5 @{ T~ p!sound!rockchip,rockchip-audio-max98090 default gVEYRON-I2S v  U U   backlight-regulatorregulator-fixed  +/  defaultbacklight_regulator  :rpanel-regulatorregulator-fixed  +  defaultpanel_regulator rvcc18-lcdregulator-fixed  +/  default vcc18_lcd backlightpwm-backlight   5 N  default 0B@ [  p  rpanelauo,b101ean01Cokay  panel-timing@         portsportendpoint rgpio-charger gpio-charger mains 4 defaultlid-switch gpio-keys defaultswitch-lid Lid 4   vccsysregulator-fixedvccsysrvcc5-host1-regulatorregulator-fixed  +4  default vcc5_host1vcc5v-otg-regulatorregulator-fixed  +4  default vcc5_host2volume-buttons gpio-keys defaultkey-volum-down Volum_down   r dkey-volum-up Volum_up   s d #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-buskeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplyti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenvactivevfront-porchvback-porchvsync-lencharger-typelinux,input-type