‘8( Tgoogle,veyron-mighty-rev5google,veyron-mighty-rev4google,veyron-mighty-rev3google,veyron-mighty-rev2google,veyron-mighty-rev1google,veyron-mightygoogle,veyronrockchip,rk3288&7Google Mightyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000/mmc@ff0c0000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12  (7@ELrf rcpu@501cpuarm,cortex-a12  (7@ELrrcpu@502cpuarm,cortex-a12  (7@ELrrcpu@503cpuarm,cortex-a12  (7@ELrropp-table-0operating-points-v2zropp-126000000 opp-216000000  opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJopp-1608000000_" opp-1704000000epopp-1800000000kI\reserved-memorydma-unusable@fe000000 oscillator fixed-clockn6xin24mr timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea   pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр EDrv biuciuciu-driveciu-sample,  @ 7resetCokayJTfw  Zdefault   mmc@ff0d0000rockchip,rk3288-dw-mshcр EEsw biuciuciu-driveciu-sample, ! @ 7resetCokayJf,BMdefault  btmrvl@2marvell,sd8897-bt &[ default mmc@ff0e0000rockchip,rk3288-dw-mshcр EFtx biuciuciu-driveciu-sample, " @ 7reset Cdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcр EGuy biuciuciu-driveciu-sample, # @ 7resetCokayJTnyBMdefault   !saradc@ff100000rockchip,saradc  $EI[ saradcapb_pclk W 7saradc-apb Cdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEAR spiclkapb_pclk" " txrx ,default #$%& Cokayec@0google,cros-ec-spi & default '-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb# 6DP;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBS spiclkapb_pclk" "txrx -default ()*+  Cdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECT spiclkapb_pclk""txrx .default ,-./ Cokay] flash@0jedec,spi-nor i2c@ff140000rockchip,rk3288-i2c  > i2cEMdefault 0Cokayp2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c  ? i2cEOdefault 1 Cdisabledi2c@ff160000rockchip,rk3288-i2c  @ i2cEPdefault 2Cokayp2,ts3a227e@3b ti,ts3a227e ;&3default 4rtrackpad@15elan,ekth3000 & default 56i2c@ff170000rockchip,rk3288-i2c  A i2cEQdefault 7 Cdisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart  7EMU baudclkapb_pclk""txrxdefault  89:Cokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart  8ENV baudclkapb_pclk""txrxdefault ;Cokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart i 9EOW baudclkapb_pclkdefault <Cokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart  :EPX baudclkapb_pclk""txrxdefault = Cdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart  ;EQY baudclkapb_pclk" " txrxdefault > Cdisableddma-controller@ff250000arm,pl330arm,primecell %@E  apb_pclkr"thermal-zonesreserve-thermal/ES?cpu-thermal/dES?tripscpu_alert0cpopassiver@cpu_alert1c$opassiverAcpu_critco criticalcooling-mapsmap0z@0map1zA0gpu-thermal/dES?tripsgpu_alert0c4opassiverBgpu_critco criticalcooling-mapsmap0zB Ctsadc@ff280000rockchip,rk3288-tsadc ( %EHZ tsadcapb_pclk  7tsadc-apbinitdefaultsleep DEDFHCokayr?ethernet@ff290000rockchip,rk3288-gmac )macirqeth_wake_irqF8Efgc]M stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B 7stmmaceth Cdisabledusb@ff500000 generic-ehci P EG#usbCokay-usb@ff520000 generic-ohci R )EG#usb Cdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 T E otgChostH #usb2-phyKCokaybusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 X E otgChosty@@ I #usb2-phyCokayzIbusb@ff5c0000 generic-ehci \ E Cdisableddma-controller@ff600000arm,pl330arm,primecell `@E  apb_pclk Cdisabledi2c@ff650000rockchip,rk3288-i2c e < i2cELdefault JCokayp2dpmic@1brockchip,rk808 xin32kwifibt_32kin&3default  KLM !N-9ER6_lNxN rregulatorsDCDC_REG1vdd_arm q qr regulator-state-mem DCDC_REG2vdd_gpu 5qrregulator-state-mem DCDC_REG3 vcc135_ddrregulator-state-mem"DCDC_REG4vcc_18w@w@rregulator-state-mem":w@LDO_REG1 vcc33_io2Z2Zr6regulator-state-mem":2ZLDO_REG3vdd_10B@B@regulator-state-mem":B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-mem SWITCH_REG1 vcc33_lcdrdregulator-state-mem LDO_REG6 vcc18_codecw@w@reregulator-state-mem LDO_REG4 vccio_sdw@2Zrregulator-state-mem LDO_REG5 vcc33_sd2Z2Zrregulator-state-mem LDO_REG8 vcc33_ccd2Z2Zregulator-state-mem LDO_REG2mic_vccw@w@regulator-state-mem i2c@ff660000rockchip,rk3288-i2c f = i2cENdefault OCokayp2 max98090@10maxim,max98090 &P mclkEqdefault Qrpwm@ff680000rockchip,rk3288-pwm hVdefault RE_Cokayrpwm@ff680010rockchip,rk3288-pwm hVdefault SE_Cokayrpwm@ff680020rockchip,rk3288-pwm h Vdefault TE_ Cdisabledpwm@ff680030rockchip,rk3288-pwm h0Vdefault UE_ Cdisabledsram@ff700000 mmio-sram ppsmp-sram@0rockchip,rk3066-smp-sram sram@ff720000#rockchip,rk3288-pmu-srammmio-sram rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd srpower-controller!rockchip,rk3288-power-controllerah ripower-domain@9 Echgfdehilkj$uVWXYZ[\]^apower-domain@11 Eopu_`apower-domain@12 Euaapower-domain@13 Eubcareboot-modesyscon-reboot-mode|RBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon tclock-controller@ff760000rockchip,rk3288-cru vE  xin24mFHjk$#gׄeрxhрxhrsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd wrFedp-phyrockchip,rk3288-dp-phyEh 24mCokayryio-domains"rockchip,rk3288-io-voltage-domainCokay6 6 6 'd 3 ?e Lusbphyrockchip,rk3288-usb-phyCokayusb-phy@320  E] phyclk  7phy-resetrIusb-phy@334 4E^ phyclk  7phy-resetrGusb-phy@348 HE_ phyclk  7phy-resetrHwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt Ep OCokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  ZET  mclkhclkftx 6default gF Cdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  Z 5ER i2s_clki2s_hclkfftxrxdefault h k Cokayrcrypto@ff8a0000rockchip,rk3288-crypto @ 0 E} aclkhclksclkapb_pclk  7crypto-rstiommu@ff900800rockchip,iommu @ E  aclkiface  Cdisablediommu@ff914000rockchip,iommu  @P E  aclkiface   Cdisabledrga@ff920000rockchip,rk3288-rga  Ej aclkhclksclk i  ilm 7coreaxiahbvop@ff930000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop i  def 7axiahbdclk jCokayportr endpoint@0  krendpoint@1  lr{endpoint@2  mrtendpoint@3  nrwiommu@ff930300rockchip,iommu  E  aclkiface i  Cokayrjvop@ff940000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop i   7axiahbdclk oCokayportr endpoint@0  prendpoint@1  qr|endpoint@2  rruendpoint@3  srxiommu@ff940300rockchip,iommu  E  aclkiface i  Cokayrodsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi @ E~d  refpclk i F Cdisabledportsport@0 endpoint@0  trmendpoint@1  urrport@1 lvds@ff96c000rockchip,rk3288-lvds @Eg  pclk_lvdslcdc v i F Cdisabledportsport@0 endpoint@0  wrnendpoint@1  xrsport@1 dp@ff970000rockchip,rk3288-dp @ bEic dppclky#dp i  o7dpFCokaydefault zportsport@0 endpoint@0  {rlendpoint@1  |rqport@1 endpoint@0  }rhdmi@ff980000rockchip,rk3288-dw-hdmi  ZF gEhmn iahbisfrcec i Cokaydefaultunwedge ~rportsportendpoint@0  rkendpoint@1  rpvideo-codec@ff9a0000rockchip,rk3288-vpu    vepuvdpuE  aclkhclk  i iommu@ff9a0800rockchip,iommu  E  aclkiface  i riommu@ff9c0440rockchip,iommu  @@@ oE  aclkiface  Cdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760 $ jobmmugpuE( i Cokay rCopp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon rbqos@ffaa0080rockchip,rk3288-qossyscon rcqos@ffad0000rockchip,rk3288-qossyscon rWqos@ffad0100rockchip,rk3288-qossyscon  rXqos@ffad0180rockchip,rk3288-qossyscon  rYqos@ffad0400rockchip,rk3288-qossyscon  rZqos@ffad0480rockchip,rk3288-qossyscon  r[qos@ffad0500rockchip,rk3288-qossyscon  rVqos@ffad0800rockchip,rk3288-qossyscon  r\qos@ffad0880rockchip,rk3288-qossyscon  r]qos@ffad0900rockchip,rk3288-qossyscon r^qos@ffae0000rockchip,rk3288-qossyscon raqos@ffaf0000rockchip,rk3288-qossyscon r_qos@ffaf0080rockchip,rk3288-qossyscon r`dma-controller@ffb20000arm,pl330arm,primecell @E  apb_pclkrfefuse@ffb40000rockchip,rk3288-efuse Eq  pclk_efusecpu-id@7 cpu_leakage@17 interrupt-controller@ffc01000 arm,gic-400  @  @ `   rpinctrlrockchip,rk3288-pinctrlFdefaultsleep gpio@ff750000rockchip,gpio-bank u QE@  /   ;PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTr3gpio@ff780000rockchip,gpio-bank x REA  /  gpio@ff790000rockchip,gpio-bank y SEB  /  M ;CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENrgpio@ff7a0000rockchip,gpio-bank z TEC  /   ;FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank { UED  /   ;UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKErgpio@ff7c0000rockchip,gpio-bank | VEE  /  A ;SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENrgpio@ff7d0000rockchip,gpio-bank } WEF  /   ;I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDrPgpio@ff7e0000rockchip,gpio-bank ~ XEG  /   ;LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDr gpio@ff7f0000rockchip,gpio-bank  YEH  /  ^ ;RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Khdmi-cec-c7 Khdmi-ddc Kr~hdmi-ddc-unwedge Krvcc50-hdmi-en Krpcfg-output-low Yrpcfg-pull-up drpcfg-pull-down qrpcfg-pull-none rpcfg-pull-none-12ma  rsuspendglobal-pwroff Krddrio-pwroff Krddr0-retention Krddr1-retention Ksuspend-l-wake Krsuspend-l-sleep Kredpedp-hpd K rzi2c0i2c0-xfer KrJi2c1i2c1-xfer Kr0i2c2i2c2-xfer K  rOi2c3i2c3-xfer Kr1i2c4i2c4-xfer Kr2i2c5i2c5-xfer Kr7i2s0i2s0-bus` Krhlcdclcdc-ctl@ Krvsdmmcsdmmc-clk Krsdmmc-cmd Krsdmmc-cd Ksdmmc-bus1 Ksdmmc-bus4@ Krsdmmc-cd-disabled Krsdmmc-cd-pin Krsdmmc-wp-pin K rsdio0sdio0-bus1 Ksdio0-bus4@ Krsdio0-cmd Krsdio0-clk Krsdio0-cd Ksdio0-wp Ksdio0-pwr Ksdio0-bkpwr Ksdio0-int Kwifienable-h Krbt-enable-l Kbt-host-wake Kbt-host-wake-l Krbt-dev-wake-sleep Krbt-dev-wake-awake Krbt-dev-wake Ksdio1sdio1-bus1 Ksdio1-bus4@ Ksdio1-cd Ksdio1-wp Ksdio1-bkpwr Ksdio1-int Ksdio1-cmd Ksdio1-clk Ksdio1-pwr K emmcemmc-clk Kremmc-cmd Kr emmc-pwr K emmc-bus1 Kemmc-bus4@ Kemmc-bus8 Kr!emmc-reset K rspi0spi0-clk K r#spi0-cs0 K r&spi0-tx Kr$spi0-rx Kr%spi0-cs1 Kspi1spi1-clk K r(spi1-cs0 K r+spi1-rx Kr*spi1-tx Kr)spi2spi2-cs1 Kspi2-clk Kr,spi2-cs0 Kr/spi2-rx Kr.spi2-tx K r-uart0uart0-xfer Kr8uart0-cts Kr9uart0-rts Kr:uart1uart1-xfer K r;uart1-cts K uart1-rts K uart2uart2-xfer Kr<uart3uart3-xfer Kr=uart3-cts K uart3-rts K uart4uart4-xfer Kr>uart4-cts K uart4-rts K tsadcotp-pin K rDotp-out K rEpwm0pwm0-pin KrRpwm1pwm1-pin KrSpwm2pwm2-pin KrTpwm3pwm3-pin KrUgmacrgmii-pins K rmii-pins Kspdifspdif-tx K rgpcfg-pull-none-drv-8ma  rpcfg-pull-up-drv-8ma d pcfg-output-high rbuttonspwr-key-l Krap-lid-int-l Krpmicpmic-int-l KrKdvs-1 K rLdvs-2 KrMrebootap-warm-reset-h K rrecovery-switchrec-mode-l K tpmtpm-int-h Kwrite-protectfw-wp-ap Kcodechp-det Krint-codec KrQmic-det K rheadsetts3a227e-int-l Kr4backlightbl_pwr_en K rbl-en Krlcdlcd-en Kravdd-1v8-disp-en K rchargerac-present-ap Krcros-ecec-int Kr'trackpadtrackpad-int Kr5usb-hosthost1-pwr-en K rusbotg-pwren-h K rbuck-5vdrv-5v Krchosen serial2:115200n8memorymemory power-button gpio-keysdefault key-power Power 3 t dgpio-restart gpio-restart 3 default  emmc-pwrseqmmc-pwrseq-emmc default rsdio-pwrseqmmc-pwrseq-simpleE  ext_clockdefault  rvcc-5vregulator-fixedvcc_5vLK@LK@   default rNvcc33-sysregulator-fixed vcc33_sys2Z2Z rvcc50-hdmiregulator-fixed vcc50_hdmi N  default vdd-logicpwm-regulator vdd_logic   { 3~psound!rockchip,rockchip-audio-max98090default  FVEYRON-I2S U m P P   backlight-regulatorregulator-fixed  default backlight_regulator  :rpanel-regulatorregulator-fixed  default panel_regulator rvcc18-lcdregulator-fixed  default  vcc18_lcd backlightpwm-backlight    - default  B@ :  O  `rpanelinnolux,n116bgeCokay ` mpanel-timingl wV  <       portsportendpoint r}gpio-charger gpio-charger mains 3default lid-switch gpio-keysdefault switch-lid Lid 3   vccsysregulator-fixedvccsysrvcc5-host1-regulatorregulator-fixed  3 default  vcc5_host1vcc5v-otg-regulatorregulator-fixed  3 default  vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplypinctrl-namespinctrl-0wp-gpioscap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,wakeup-pindisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type