8( *chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV acpu@501cpuarm,cortex-a12'@5<rV acpu@502cpuarm,cortex-a12'@5<rV acpu@503cpuarm,cortex-a12'@5<rV aopp-table-0operating-points-v2iaopp-126000000t{ opp-216000000t { opp-312000000t{ opp-408000000tQ{ opp-600000000t#F{ opp-696000000t)|{~opp-816000000t0,{B@opp-1008000000t<{opp-1200000000tG{opp-1416000000tTfr{Oopp-1512000000tZJ{ opp-1608000000t_"{preserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24ma timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshc р 5Drvbiuciuciu-driveciu-sample  @&reset2okay9CUfxdefault mmc@ff0d0000rockchip,rk3288-dw-mshc р 5Eswbiuciuciu-driveciu-sample ! @&reset 2disabledmmc@ff0e0000rockchip,rk3288-dw-mshc р 5Ftxbiuciuciu-driveciu-sample "@&reset 2disabledmmc@ff0f0000rockchip,rk3288-dw-mshc р 5Guybiuciuciu-driveciu-sample #@&reset2okay9Cdefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW &saradc-apb 2disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk%  *txrx ,default 2disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk% *txrx -default ! 2disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk%*txrx .default"#$% 2disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault&2okayak8963@dasahi-kasei,ak8975 &'default(4?l3g4200d@69st,l3g4200d-gyroJi4Zmma8452@1d fsl,mma8452&'default)i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault*2okayi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault+2okayi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault,2okayasserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7gq5MUbaudclkapb_pclk%*txrxdefault-2okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8gq5NVbaudclkapb_pclk%*txrxdefault.2okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9gq5OWbaudclkapb_pclkdefault/2okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :gq5PXbaudclkapb_pclk%*txrxdefault02okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;gq5QYbaudclkapb_pclk%  *txrxdefault12okaydma-controller@ff250000arm,pl330arm,primecell%@~5 apb_pclkathermal-zonesreserve-thermal2cpu-thermald2tripscpu_alert0ppassivea3cpu_alert1$passivea4cpu_crit_ criticalcooling-mapsmap030 map140 gpu-thermald2tripsgpu_alert0ppassivea5gpu_crit_ criticalcooling-mapsmap05  6tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk &tsadc-apbinitdefaultsleep78$7.D9Qs2okayha2ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqD985fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB &stmmaceth2okay:rgmiiinput ; 'B@<default=-06usb@ff500000 generic-ehciP 5?>Dusb 2disabledusb@ff520000 generic-ohciR )5?>Dusb 2disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otgNhost?? Dusb2-phyV 2disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgNotgm@@ ?@ Dusb2-phy2okayusb@ff5c0000 generic-ehci\ 5 2disableddma-controller@ff600000arm,pl330arm,primecell`@~5 apb_pclk 2disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultA2okaypmic@1brockchip,rk808&BdefaultCDxin32krk808-clkout2EEEEEEF ,9EFZregulatorsDCDC_REG1Sgy qpvdd_arma regulator-state-memDCDC_REG2Sgy Pvdd_gpuregulator-state-memB@DCDC_REG3Sgvcc_ddrregulator-state-memDCDC_REG4Sgy2Z2Zvcc_ioaregulator-state-mem2ZLDO_REG1Sgy2Z2Zvcc_lana:regulator-state-mem2ZLDO_REG2Sgyw@2Z vccio_sdaregulator-state-memLDO_REG3SgyB@B@vdd_10regulator-state-memB@LDO_REG4Sgyw@w@ vcc18_lcdregulator-state-memw@LDO_REG5Syw@2Zldo5LDO_REG6SgyB@B@ vdd10_lcdregulator-state-memB@LDO_REG7Sgyw@w@vcc_18aFregulator-state-memw@LDO_REG8Sgy2Z2Zvcca_33aZregulator-state-mem2ZSWITCH_REG1Sg vccio_wla\regulator-state-memSWITCH_REG2Sgvcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultG2okaypwm@ff680000rockchip,rk3288-pwmhdefaultH5_ 2disabledpwm@ff680010rockchip,rk3288-pwmhdefaultI5_ 2disabledpwm@ff680020rockchip,rk3288-pwmh defaultJ5_ 2disabledpwm@ff680030rockchip,rk3288-pwmh0defaultK5_ 2disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsapower-controller!rockchip,rk3288-power-controllerh a`power-domain@9 5chgfdehilkj$$LMNOPQRSTpower-domain@11 5op$UVpower-domain@12 5$Wpower-domain@13 5$XYreboot-modesyscon-reboot-mode+2RB>RBLRB \RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24mD9hHjk$u#gׄeрxhрxhasyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwa9edp-phyrockchip,rk3288-dp-phy5h24m 2disabledapio-domains"rockchip,rk3288-io-voltage-domain2okayZ[: \usbphyrockchip,rk3288-usb-phy2okayusb-phy@320 5]phyclk &phy-reseta@usb-phy@33445^phyclk &phy-reseta>usb-phy@348H5_phyclk &phy-reseta?watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O 2disabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclk%]*tx 6default^D9 2disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclk%]]*txrxdefault_(C 2disabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk &crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkiface] 2disablediommu@ff914000rockchip,iommu @P 5 aclkiface]j 2disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk` ilm &coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop` def &axiahbdclka2okayporta endpoint@0batendpoint@1caqendpoint@2dakendpoint@3eaniommu@ff930300rockchip,iommu 5 aclkiface` ]2okayaavop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop`  &axiahbdclkf2okayporta endpoint@0gauendpoint@1harendpoint@2ialendpoint@3jaoiommu@ff940300rockchip,iommu 5 aclkiface` ]2okayafdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk` D9 2disabledportsport@0endpoint@0kadendpoint@1laiport@1lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcm` D9 2disabledportsport@0endpoint@0naeendpoint@1oajport@1dp@ff970000rockchip,rk3288-dp@ b5icdppclk?pDdp` o&dpD9 2disabledportsport@0endpoint@0qacendpoint@1rahport@1hdmi@ff980000rockchip,rk3288-dw-hdmiqD9 g5hmniahbisfrcec` 2okaysportsportendpoint@0tabendpoint@1uagvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkv` iommu@ff9a0800rockchip,iommu 5 aclkiface]` aviommu@ff9c0440rockchip,iommu @@@ o5 aclkiface] 2disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5w`  2disableda6opp-table-1operating-points-v2awopp-100000000t{~opp-200000000t {~opp-300000000t{B@opp-400000000tׄ{opp-600000000t#F{qos@ffaa0000rockchip,rk3288-qossyscon aXqos@ffaa0080rockchip,rk3288-qossyscon aYqos@ffad0000rockchip,rk3288-qossyscon aMqos@ffad0100rockchip,rk3288-qossyscon aNqos@ffad0180rockchip,rk3288-qossyscon aOqos@ffad0400rockchip,rk3288-qossyscon aPqos@ffad0480rockchip,rk3288-qossyscon aQqos@ffad0500rockchip,rk3288-qossyscon aLqos@ffad0800rockchip,rk3288-qossyscon aRqos@ffad0880rockchip,rk3288-qossyscon aSqos@ffad0900rockchip,rk3288-qossyscon aTqos@ffae0000rockchip,rk3288-qossyscon aWqos@ffaf0000rockchip,rk3288-qossyscon aUqos@ffaf0080rockchip,rk3288-qossyscon aVdma-controller@ffb20000arm,pl330arm,primecell@~5 apb_pclka]efuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   apinctrlrockchip,rk3288-pinctrlD9gpio@ff750000rockchip,gpio-banku Q5@aBgpio@ff780000rockchip,gpio-bankx R5Agpio@ff790000rockchip,gpio-banky S5Bgpio@ff7a0000rockchip,gpio-bankz T5Cgpio@ff7b0000rockchip,gpio-bank{ U5Da;gpio@ff7c0000rockchip,gpio-bank| V5Egpio@ff7d0000rockchip,gpio-bank} W5Fgpio@ff7e0000rockchip,gpio-bank~ X5Gagpio@ff7f0000rockchip,gpio-bank Y5Ha'hdmihdmi-cec-c0xhdmi-cec-c7xhdmi-ddc xxhdmi-ddc-unwedge yxpcfg-output-low aypcfg-pull-up azpcfg-pull-down a{pcfg-pull-none -axpcfg-pull-none-12ma - : a|suspendglobal-pwroffxaDddrio-pwroffxddr0-retentionzddr1-retentionzedpedp-hpd {i2c0i2c0-xfer xxaAi2c1i2c1-xfer xxa&i2c2i2c2-xfer  x xaGi2c3i2c3-xfer xxa*i2c4i2c4-xfer xxa+i2c5i2c5-xfer xxa,i2s0i2s0-bus`xxxxxxa_lcdclcdc-ctl@xxxxamsdmmcsdmmc-clkxa sdmmc-cmdzasdmmc-cdzasdmmc-bus1zsdmmc-bus4@zzzzasdmmc-pwr xasdio0sdio0-bus1zsdio0-bus4@zzzzsdio0-cmdzsdio0-clkxsdio0-cdzsdio0-wpzsdio0-pwrzsdio0-bkpwrzsdio0-intzsdio1sdio1-bus1zsdio1-bus4@zzzzsdio1-cdzsdio1-wpzsdio1-bkpwrzsdio1-intzsdio1-cmdzsdio1-clkxsdio1-pwr zemmcemmc-clkxaemmc-cmdzaemmc-pwr zaemmc-bus1zemmc-bus4@zzzzemmc-bus8zzzzzzzzaspi0spi0-clk zaspi0-cs0 zaspi0-txzaspi0-rxzaspi0-cs1zspi1spi1-clk zaspi1-cs0 za!spi1-rxza spi1-txzaspi2spi2-cs1zspi2-clkza"spi2-cs0za%spi2-rxza$spi2-tx za#uart0uart0-xfer zxa-uart0-ctszuart0-rtsxuart1uart1-xfer z xa.uart1-cts zuart1-rts xuart2uart2-xfer zxa/uart3uart3-xfer zxa0uart3-cts zuart3-rts xuart4uart4-xfer zxa1uart4-cts zuart4-rts xtsadcotp-pin xa7otp-out xa8pwm0pwm0-pinxaHpwm1pwm1-pinxaIpwm2pwm2-pinxaJpwm3pwm3-pinxaKgmacrgmii-pinsxxxx||||xxx ||xxa=rmii-pinsxxxxxxxxxxspdifspdif-tx xa^ak8963comp-intza(buttonspwrbtnza}dvpdvp-pwrxairir-intza~mma8452gsensor-intza)pmicpmic-intzaCmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmaca<gpio-keys gpio-keys Idefault}key-power TB Zt eGPIO Key Power k |dir-receivergpio-ir-receiver TBdefault~flash-regulatorregulator-fixed vcc_flashyw@w@ asdmmc-regulatorregulator-fixed  defaultvcc_sdy2Z2Z  avsys-regulatorregulator-fixedvcc_sysyLK@LK@SgaEvcc18-dvp-regulatorregulator-fixed vcc18-dvpyw@w@ a[vcc28-dvp-regulatorregulator-fixed  Bdefault vcc28_dvpy**S a #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removable#io-channel-cellsdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high